Digital Integrated Circuits © Prentice Hall 2000InterconnectLecture 24Dealing withInterconnectDigital Integrated Circuits © Prentice Hall 2000InterconnectAdministrivia Project phase 2 extended till Th 5pm.» Halt all efforts and work on your report! No regrades of Midterm 2 after next Tu.Digital Integrated Circuits © Prentice Hall 2000InterconnectToday’s Lecture Dealing with capacitive interconnect Dealing with resistive interconnectDigital Integrated Circuits © Prentice Hall 2000InterconnectCOPING WITHINTERCONNECTDigital Integrated Circuits © Prentice Hall 2000InterconnectImpact of Interconnect Parasitics• Reduce Reliability• Affect PerformanceClasses of Parasitics• Capacitive•Resistive•InductiveDigital Integrated Circuits © Prentice Hall 2000InterconnectINTERCONNECTDealing with CapacitanceDigital Integrated Circuits © Prentice Hall 2000InterconnectCapacitiveCrosstalkDynamic NodeVDDPDNIn1In2In3CLKCYCXYYX2.5 V0 VCLK3x1µm overlap: 0.19 V disturbanceDigital Integrated Circuits © Prentice Hall 2000InterconnectCapacitiveCrosstalkDriven Node0 0.2 0.4 0.6 0.8 1x 10-900.050.10.150.20.250.30.350.40.450.5V (Volt)t(sec)YXCXYCYVXRYτXY=RY(CXY+CY)trKeep time-constant smaller than rise timeDigital Integrated Circuits © Prentice Hall 2000InterconnectDelay DegradationCc- Impact of neighboring signalactivity on switching delay- When neighboring lines switchin opposite direction of victimline, delay increasesMiller Effect- Both terminals of capacitor are switched in opposite directions(0 → Vdd,Vdd→ 0)- Effective voltage is doubled and additional charge is needed(from Q=CV)Digital Integrated Circuits © Prentice Hall 2000InterconnectInterconnect ProjectionsLow-k dielectricsBoth delay and power are reduced by dropping interconnectcapacitanceTypes of low-k materials include: inorganic (SiO2), organic(Polyimides) and aerogels (ultra low-k)The numbers below are on theconservative side of the NRTS roadmapGeneration 0.25µm0.18µm0.13µm0.1µm0.07µm0.05µmDielectricConstant3.3 2.7 2.3 2.0 1.8 1.5εεεεDigital Integrated Circuits © Prentice Hall 2000InterconnectHow to Battle CapacitiveCrosstalkSubstrate (GND)GNDShieldinglayerVDDGNDShieldingwireAvoid large crosstalk cap’sAvoid floating nodesIsolate sensitive nodesControl rise/fall timesShield!Differential signallingDigital Integrated Circuits © Prentice Hall 2000InterconnectStructured and Predictable InterconnectSSSVVSGSSVGVExample: Dense Wire Fabric (DWF) [Khatri, DAC99]Trade-off:• Cross-coupling capacitance 40x lower, 2% delay variation• Increase in area and overall capacitanceDigital Integrated Circuits © Prentice Hall 2000InterconnectDriving Large CapacitancesVDDVinVoutCLtpHL=CLVswing/2IavTransistorSizingDigital Integrated Circuits © Prentice Hall 2000InterconnectUsing Cascaded BuffersC2C1CiCL1uu2uN-1In Outuopt=eDigital Integrated Circuits © Prentice Hall 2000Interconnecttpin function of u and x1.0 3.0 5.0 7.0u0.020.040.060.0u/ln(u)x=10x=100x=1000x=10,000Digital Integrated Circuits © Prentice Hall 2000InterconnectImpact of Cascading BuffersDigital Integrated Circuits © Prentice Hall 2000InterconnectOutput Driver DesignDigital Integrated Circuits © Prentice Hall 2000InterconnectHow to Design Large TransistorsG(ate)S(ource)D(rain)MultipleContactsSSGD(a) small transistors in parallel(b) circular transistorsDigital Integrated Circuits © Prentice Hall 2000InterconnectBonding Pad DesignBonding PadOutInVDDGND100 µmGNDOutDigital Integrated Circuits © Prentice Hall 2000InterconnectReducing the swingtpHL = CL Vswing/2Iav• Reducing the swing potentially yields linearreduction in delay• Also results in reduction in power dissipation• Requires use of “sense amplifier” to restore signal levelDigital Integrated Circuits © Prentice Hall 2000InterconnectCharge Redistribution AmplifierM1M2 M3VrefVBVACBCA(a)0.0 1.002.003.00time (nsec)0.01.02.03.04.05.0VVBVAVinVref=3VDigital Integrated Circuits © Prentice Hall 2000InterconnectPrecharged BusIn1.fVDDIn2.fBusCbusM1M2VDDOutCoutM3M4f0510t (nsec)-1.01.03.05.0VVbusVsymfVasymCbus=1pFDigital Integrated Circuits © Prentice Hall 2000InterconnectTristate BuffersInVDDEnEnOutVDDOutInEnEnDigital Integrated Circuits © Prentice Hall 2000InterconnectINTERCONNECTDealingwithResistanceDigital Integrated Circuits © Prentice Hall 2000InterconnectRI Introduced NoiseVDDXIIR’RVDD-∆V’∆V∆VφpreDigital Integrated Circuits © Prentice Hall 2000InterconnectPower and Ground DistributionGNDVDDLogicGNDVDDLogicGNDVDD(a) Finger-shaped network (b) Network with multiple supply pinsDigital Integrated Circuits © Prentice Hall 2000InterconnectResistance and the PowerDistribution ProblemSource: Simplex• Requires fast and accurate peak current prediction• Heavily influenced by packaging technologyBeforeAfterDigital Integrated Circuits © Prentice Hall 2000InterconnectElectromigration (1)Limits dc-current to 1 mA/µmDigital Integrated Circuits © Prentice Hall 2000InterconnectElectromigration (2)Digital Integrated Circuits © Prentice Hall 2000InterconnectThe Impact of ResistivityCN-1CNC2R1R2C1TrVinRN-1RN0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L Diffused signalpropagationDelay ~ L2The distributed rc-lineDigital Integrated Circuits © Prentice Hall 2000InterconnectThe Global Wire Problem(((())))outwwdoutdwwdCRCRCR693.0CR377.0T ++++++++++++====ChallengesNo further improvements to be expected after theintroduction of Copper (superconducting, optical?)Design solutions» Use of fat wires» Insert repeaters — but might become prohibitive (power, area)» Efficient chip floorplanningTowards “communication-based” design» How to deal with latency?» Is synchronicity an absolute necessity?Digital Integrated Circuits © Prentice Hall 2000InterconnectReducing RC-delayRepeaterDigital Integrated Circuits © Prentice Hall 2000InterconnectArchitecture Must Evolve to Fit theLandscape20 Clocks90,000tracksLocal, parallel operationsHigh bandwidthLow latency &Low powerGlobal operationsLow bandwidthHigh latency &High powerSource: Bill Dally, StanfordDigital Integrated Circuits © Prentice Hall 2000InterconnectInterconnect:# of Wiring Layers# of metal layers is steadily increasing due to:• Increasing die size and device count: we need more wires and longer wires to connect everything• Rising need for a
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