Logical Effort*:Designing for Speed on the Back of an EnvelopeDavid [email protected], 1998Stanford UniversityStanford, CA* Based on a book by Ivan Sutherland, Bob Sproull, and David HarrisLELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Logical Effort David Harris Page 2 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Outline❏Introduction❏ Delay in a Logic Gate❏ Multi-stage Logic Networks❏ Choosing the Best Number of Stages❏ Example❏ SummaryLogical Effort David Harris Page 3 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891IntroductionChip designers face a bewildering array of choices.❏ What is the best circuit topology for a function?❏ How large should the transistors be?❏ How many stages of logic give least delay?Logical Effort is a method of answering these questions:❏ Uses a very simple model of delay❏ Back of the envelope calculations and tractable optimization❏ Gives new names to old ideas to emphasize remarkable symmetriesWho cares about logical effort?❏ Circuit designers waste too much time simulating and tweaking circuits❏ High speed logic designers need to know where time is going in their logic❏ CAD engineers need to understand circuits to build better tools???Logical Effort David Harris Page 4 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891ExampleBen Bitdiddle is the memory designer for the Motoroil 68W86, an embeddedprocessor for automotive applications. Help Ben design the decoder for aregister file:Decoder specification:❏ 16 word register file❏ Each word is 32 bits wide❏ Each bit presents a load of 3 unit-sized transistors❏ True and complementary inputs of address bitsa<3:0> are available❏ Each input may drive 10 unit-sized transistorsBen needs to decide:❏ How many stages to use?❏ How large should each gate be?❏ How fast can the decoder operate?Register File4:16 Decoder16 words32 bitsa<3:0>a<3:0>16Logical Effort David Harris Page 5 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Outline❏Introduction❏ Delay in a Logic Gate❏ Multi-stage Logic Networks❏ Choosing the Best Number of Stages❏ Example❏ SummaryLogical Effort David Harris Page 6 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Delay in a Logic GateLet us express delays in a process-independent unit:Delay of logic gate has two components:Effort delay again has two components:❏ Logical effort describes relative ability of gate topology to deliver current(defined to be 1 for an inverter)❏ Electrical effort is the ratio of output to input capacitanceτ20≈psin 0.25 µmtechnologyddabsτ-----------=dfp+=effort delay, a.k.a. stage effortparasitic delayfgh=logical effortelectrical effort = Cout/Cinelectrical effortis sometimescalled“fanout”Logical Effort David Harris Page 7 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Delay Plots❏❏Delay increases with electrical effort❏ More complex gates have greater logical effort and parasitic delayinverter2-input NAND54321543261parasitic delayeffortdelayElectrical effort: h = Cout / CinNormalized delay: dg =p =d =g =p =d =dfp+gh p+==How about a2-input NOR?Logical Effort David Harris Page 8 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Computing Logical EffortDEF: Logical effort is the ratio of the input capacitance of a gate to the inputcapacitance of an inverter delivering the same output current.❏ Measured from delayvs. fanout plots of simulated or measured gates❏ Or estimated, counting capacitance in units of transistor width:21ax2222xab4411abxInverter:Cin = 3g = 1 (def)NAND2:Cin = 4g = 4/3NOR2:Cin = 5g = 5/3Logical Effort David Harris Page 9 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891A Catalog of GatesTable 1: Logical effort of static CMOS gatesGate typeNumber of inputs12345ninverter 1NAND 4/3 5/3 6/3 7/3 (n+2)/3NOR 5/3 7/3 9/3 11/3 (2n+1)/3multiplexer 22222XOR, XNOR 4 12 32Table 2: Parasitic delay of static CMOS gatesGate type Parasitic delayinverterpinvn-input NANDnpinvn-input NORnpinvn-way multiplexer 2npinv2-input XOR, XNOR 4npinvparasitic delaysdepend on diffusioncapacitancepinv1≈Logical Effort David Harris Page 10 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891ExampleEstimate the frequency of anN-stage ring oscillator:Logical Effort:Electrical Effort:Parasitic Delay:Stage Delay:Oscillator Frequency:g=h=p=d=F=Logical Effort David Harris Page 11 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891ExampleEstimate the delay of a fanout-of-4 (FO4) inverter:Logical Effort:Electrical Effort:Parasitic Delay:Stage Delay:dg=h=p=d=Logical Effort David Harris Page 12 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Outline❏Introduction❏ Delay in a Logic Gate❏ Multi-stage Logic Networks❏ Choosing the Best Number of Stages❏ Example❏ SummaryLogical Effort David Harris Page 13 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Multi-stage Logic NetworksLogical effort extends to multi-stage networks:❏ Path Logical Effort:❏ Path Electrical Effort:❏ Path Effort:Can we write ?20xyz10g1 = 1h1 = x/10g2 = 5/3h2 = y/xg3 = 4/3h3 = z/yg4 = 1h4 = 20/zGgi∏=HCout (path)Cin (path)----------------------=Hhi∏=because we don’tknowhi until thedesign is doneDon’t defineFfi∏gihi∏==FGH=Logical Effort David Harris Page 14 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Branching EffortNo! Consider circuits that branch:GHGHh1h2F====== = GH?515159090Logical Effort David Harris Page 15 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Delay in Multi-stage NetworksWe can now compute the delay of a multi-stage network:❏ Path Effort Delay:❏ Path Parasitic Delay:❏ Path Delay:We can prove that delay is minimized when each stage bears the same effort:Therefore, the minimum delay of anN-stage path is:❏ This is a key result of logical effort. Lowest possible path delay can be foundwithout even calculating the sizes of each gate in the path.DFfi∑=PFpi∑=DFdi∑DFP+==fˆgihiF1N⁄==NF1N⁄P+Logical Effort David Harris Page 16 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891Determining Gate SizesGate sizes can be found by starting at the end of the path and working backward.❏ At each gate, apply the capacitance transformation:❏ Check your work by verifying that the input capacitance specification is satis-fied at the beginning of the path.CiniCoutigi•fˆ-----------------------=Logical Effort David Harris Page 17 of 38LELAND STANFORD JUNIOR UNIVERSITYORGANIZED 1891ExampleSelect gate sizesy andz to minimize
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