EE1411EECS1411Lecture #16EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsLecture 16Lecture 16Pass Transistor LogicPass Transistor LogicEE1412EECS1412Lecture #16AnnouncementsAnnouncements Homework 6 Due Friday April Project Phase 1 is Under Way Questions CSD notationEE1413EECS1413Lecture #16CSD Notation and CSD Notation and SubtractorsSubtractorsEE1414EECS1414Lecture #16Class MaterialClass Material Last lecture Adders Today’s lecture Ratioed Logic Pass Transistor Logic Reading (Chapter 6)EE1415EECS1415Lecture #16RatioedRatioedLogicLogicEE1416EECS1416Lecture #16Why Why RatioedRatioedLogic?Logic?EE1417EECS1417Lecture #16RatioedRatioedLogicLogicVDDVSSPDNIn1In2In3FRLLoadVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNResistiveDepletionLoadPMOSLoad(a) resistive load (b) depletion load NMOS (c) pseudo-NMOSVT < 0Goal: build gates faster/smaller than staticcomplementary CMOSEE1418EECS1418Lecture #16Ratioed LogicRatioed Logic Spend power for speed What is the best gate topology for this? (NAND vs NOR) DC characteristics: VOH= VDD VOLdepends on PMOS to NMOS ratioWWW WEE1419EECS1419Lecture #16PseudoPseudo--NMOS VTCNMOS VTC0.0 0.5 1.0 1.5 2.0 2.50.00.51.01.52.02.53.0Vin[V]Vout[V]W/Lp = 4W/Lp = 2W/Lp = 1W/Lp = 0.25W/Lp = 0.5EE14110EECS14110Lecture #16Ratioed Logic LERatioed Logic LE Rising and falling delays aren’t the same Calculate LE for the two edges separately For tpLH: Cgate= WCGCinv= (3/2)WCGLELH=EE14111EECS14111Lecture #16Ratioed Logic LE (pullRatioed Logic LE (pull--down edge)down edge)WWW W What is LE for tpHL? Switch model would predict Reff= Rn||Rp Would that give the right answer for LE?EE14112EECS14112Lecture #16Response on Falling EdgeResponse on Falling Edge Time constant is smaller, but it takes more time to complete 50% VDDtransient (arguably) Rp actually takes some current away from discharging CRpRnCvo(t)0123400.51vo(t)/VDDtRp=RnRp=2RnRp=4RnRp=∞CRpRnRpRn⋅+⋅=ττ/1)(tDDoeRpRnRnRpRnRnVtv−⎟⎟⎠⎞⎜⎜⎝⎛+−++=EE14113EECS14113Lecture #16RatioedRatioedLogic PullLogic Pull--down Delaydown Delay Think in terms of the current driving Cload When you have a conflict between currents Available current is the difference between the two In pseudo-nMOS case: (Works because Rp >> Rn for good noise margin)()1drive drive1RnR= R=11-Rn-Rn RpRpEE14114EECS14114Lecture #16Ratioed Logic LE (pullRatioed Logic LE (pull--down edge)down edge) For tpHL(assuming Rsqp= 2Rsqn): Rgate= Rn/(1-Rn/Rp) = 2Rn Rinv= Rn Cgate= WCGCinv= 3WCG LEHL= LE is lower than an inverter! But have static power dissipation…WWW W2WWEE14115EECS14115Lecture #16Improved LoadsImproved LoadsABCDFCLM1M2M1 >> M2EnableVDDAdaptive LoadEE14116EECS14116Lecture #16Improved Loads (2)Improved Loads (2)VDDVSSFOutVDDVSSF_bOutAABBM1 M2Differential Cascode Voltage Switch Logic (DCVSL)EE14117EECS14117Lecture #16DCVSL Transient ResponseDCVSL Transient Response0 0.2 0.4 0.6 0.8 1.0-0.50.51.52.5Time [ns]Vol ta ge[V]A BA BA,BA,BEE14118EECS14118Lecture #16DCVSL Example1DCVSL Example1EE14119EECS14119Lecture #16DCVSL Example2DCVSL Example2BAABBBOutOutXOR-NXOR gateXOR/XNOR gateEE14120EECS14120Lecture #16PassPass--TransistorTransistorLogicLogicEE14121EECS14121Lecture #16PassPass--Transistor LogicTransistor LogicInputsSwitchNetworkOutOutABBB• N transistors• No static consumptionEE14122EECS14122Lecture #16Example: AND GateExample: AND GateBBAF = AB0EE14123EECS14123Lecture #16NMOSNMOS--Only LogicOnly LogicVDDInOutx0.5μm/0.25μm0.5μm/ 0.2 5μm1.5μm/ 0.2 5μm0 0.5 1 1.5 20.01.02.03.0Time [ns]Voltage[V]xOutInEE14124EECS14124Lecture #16NMOSNMOS--only Switchonly SwitchA = 2.5 VBC = 2.5VCLA = 2.5 VC = 2.5 VBM2M1MnThreshold voltage loss causesstatic power consumptionVBdoes not pull up to 2.5V, but 2.5V -VTNNMOS has higher threshold than PMOS (body effect)EE14125EECS14125Lecture #16NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring TransistorM2M1MnMrOutABVDDVDDLevel RestorerX• Advantage: Full Swing• Restorer adds capacitance, takes away pull down current at X• Ratio problemEE14126EECS14126Lecture #16Restorer SizingRestorer Sizing0 100 200 300 400 5000.01.02.0W/Lr=1.0/0.25 W/Lr=1.25/0.25 W/Lr=1.50/0.25 W/Lr=1.75/0.25 Voltage [V]Time [ps]3.0•Upper limit on restorer size•Pass-transistor pull-downcan have several transistors in stackEE14127EECS14127Lecture #16Pass Transistor Logic LEPass Transistor Logic LE What is LE of “gate” shown below for A and B inputs? Hint: Can you answer this question with only the information shown below?EE14128EECS14128Lecture #16Pass Transistor Logic LEPass Transistor Logic LE In CMOS, a “gate” is defined only when trace a connection all the way back to a supply Otherwise don’t know what drive resistance really isEE14129EECS14129Lecture #16Pass Transistor Logic LEPass Transistor Logic LEEE14130EECS14130Lecture #16Complementary Pass Transistor LogicComplementary Pass Transistor LogicABABBBB BABABF=ABF=ABF=A+BF=A+BB BAAAAF=A⊕ΒÝF=A⊕ΒÝOR/NOREXOR/NEXORAND/NANDFFPass-TransistorNetworkPass-TransistorNetworkAABBAABBInverse(a)(b)EE14131EECS14131Lecture #16CPL Level RestoreCPL Level RestoreEE14132EECS14132Lecture #16Solution 2: Transmission GateSolution 2: Transmission GateABCCABCCBCLC = 0 VA = 2.5 VC = 2.5 VEE14133EECS14133Lecture #16Resistance of Transmission GateResistance of Transmission GateVout0 V2.5 V2.5 VRnRp0. 0 1. 0 2. 00 10 20 30 Vout, VResistance, ohmsRnRpRn || RpEE14134EECS14134Lecture #16PassPass--Transistor Based MultiplexerTransistor Based MultiplexerAM2M1BSSSFVDDGNDVDDIn1In2SSSSEE14135EECS14135Lecture #16Transmission Gate XORTransmission Gate XOREE14136EECS14136Lecture #16Delay in Transmission Gate NetworksDelay in Transmission Gate NetworksV1 Vi-1C2.52.500Vi Vi+1CC2.50Vn-1 VnCC2.50InV1ViVi+1CVn-1VnCCInReqReqReqReqCC(a)(b)CReqReqCCReqCCReqReqC CReqCInm(c)EE14137EECS14137Lecture #16Delay OptimizationDelay OptimizationEE14138EECS14138Lecture #16Transmission Gate Full AdderTransmission Gate Full AdderABPCiVDDAAAVDDCiAPABVDDVDDCiCiCoSCiPPPPPSum GenerationCarry GenerationSetupSimilar delays for sum and carryEE14139EECS14139Lecture #16Next LectureNext Lecture Dynamic
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