UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on Nov. 13th, 2009. Elad Alon FALL 2009 PROJECT PHASE III EECS 141 Project plan due Sat. Nov 21st by email Poster presentation due Wed. Dec. 2nd @ BWRC Final report due Mon. Dec. 7th @ 240 Cory 1. Putting it all together The principal goal of Phase III of the project is to complete the entire programmable functional unit. For convenience, the programmable functional unit’s block diagram is repeated below. This phase of the project allows for the most creativity, but will also be the most time consuming of the three phases. We strongly recommend that you START EARLY in order to allow yourself plenty of time to design, optimize, and assemble the complete functional unit. 2. Design Optimization In the previous two phases, explicit instructions were given on how to implement and assemble the adder, decoder, and SRAM cell. As with these previous phases, the primary constraint on your design is that it must function correctly. However, beyond building a functional design, in this final phase of the project it will be up to you to decide which design metrics you’d like to focus on optimizing. For example, you can try to build the fastest functional unit possible,minimize the unit’s power consumption, pack the design into the smallest area, or shoot for a balance of two or three of these metrics. No matter which of these goals you pick, your final design should include substantial optimizations/modifications to at least one out of the three principal blocks: the adder, the decoder, and the SRAM array. Several examples of potential optimizations are described below; note however that these are only a few of the possible optimizations that can be made to your design. The optimizations you decide to apply are limited only by your own creativity, but you do need to adhere to the constraints and guidelines on input capacitance, rise/fall times, margins, etc. provided in the project phase I handout. 1. Re-organize the SRAM array Although the SRAMs used in the functional unit are logically 32x5 (i.e., they store 32 distinct 5-bit words), this may not be the optimal physical organization for the array. For example, the SRAM could be re-organized into a more square configuration (16x10 in the example shown below) by introducing a column multiplexor. This obviously has implications on both the lengths of the bitline and wordline wires as well as the decoder implementation, so if you try this optimization you should be sure to analyze the impact of the array organization on the metrics you care about. 2. Use more advanced logic styles (domino, pass-transistor, pseudo-NMOS) Instead of using static CMOS logic to implement the adder and decoder, you can explore the use of alternate logic styles. For example, you might try to implement the decoder using domino logic, or use a Manchester carry chain for the adder. Remember there are almost always tradeoffs when choosing between logic styles, so it will be up to you to determine which logic style best fits with your original optimization goals.3. Use a lower VDD and/or add one or more extra power supplies to reduce power Reducing the supply voltage of a digital circuit is one of the most effective means for trading off performance for reduced power consumption, and thus one option you can explore is to lower the VDD for the entire functional unit. If you are shooting for a balance of speed and power, you can also explore using a separate supply voltage for various pieces of the design. For example, you might choose to use a lower voltage in the final decode drivers in order to reduce their switching power without significantly impacting the overall delay. Note that if you use a lower supply voltage somewhere in your design, you should re-characterize the transistor parameters (CG, CD, Rsq) at this new voltage. 4. Redesign the decoder and the adder with only the decoder’s Cin constrained to 6fF and the output load of 30fF Since you are doing the design of the whole unit, your only constraint on Cin is that the address inputs of the decoder must have less than 6fF of capacitance. In other words, you can make the input capacitance of your adder whatever you would like it to be. This allows you to resize the adder or even completely change its logical topology. However, note that each output of the adder still has to drive the capacitive load of 30fF. 5. Redesign the SRAM cell for improved area, speed, and/or power In phase I of the project, you were given a schematic and layout of a functional 6-T SRAM cell. This cell is reasonably well optimized in terms of area and sizing, but in this phase of the project you are free to design your own cell to try to improve its characteristics. If you do decide to redesign the cell, you must meet the following requirements: the voltage rise in the cell during a read should be no higher than 150mV, and the worst-case cell voltage during a write must be less than 200mV. In your final report, you should state what your objectives were for the optimizations you chose to apply. Whether you optimized for speed, power, layout area, or some combination of the three, please be very clear about the methods you used to improve your design. A big part of the judging of your project will be based on how well the optimizations you made actually coincide with your stated goal. Whichever optimizations you choose to do, remember that you do need to complete an LVS and DRC clean layout of the entire design – including the two 32x5 SRAM arrays, the adder, the decoders, and two additional peripheral circuits described bellow. 1. Pre-charge Transistors After every read operation, the bitlines need to be pre-charged back to VDD – this is easily achieved by connecting a PMOS pre-charge transistor to each of the bitlines. Figure 2 shows a schematic of the pre-charge transistors connected to one column of the SRAM. Typically, the pre-charge transistors would be physically placed at the top of the SRAM array, so the dimensions of the cell containing these devices should match the width of the SRAM cell. You are free to size the pre-charge transistors as you like, but you must make sure that the time it takes for the bitlines to get pre-charged to within 10% of VDD is less than the total critical path delay through your decoder.2. Output buffers In order to
View Full Document
Unlocking...