UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on Feb 2, 2004 by Gang Zhou ([email protected]) Jan Rabaey Homework #3 EECS141 Due Thursday, February 12, 5pm @558 Cory Problem 1 – VTC of Inverter a) Figure 1a depicts the Id – VOUT curve of a typical NMOS transistor Figure 1b depicts the Id – VOUT curve of a typical PMOS transistor Assume we use these FETs to create a CMOS inverter. Using this family of curves, graph the VTC, and calculate VM, VIL, and VIH. Top: Figure 1a, Bottom: Figure 1b b) If we increase the W/L ratio of the pull-down NMOS (leaving the PMOS size fixed), in which direction will the VTC shift? VGS = 2.5V VGS = 2.0V VGS = 1.5V VGS = 1.0V VGS =0.5V VGS = 0V VGS = -2.5V VGS = -2.0V VGS = -1.5V VGS = -1.0V VGS = -0.5V VGS = 0Vc) If instead, we increase the W/L ratio of the pull-up PMOS (and leave the NMOS the original size), in which direction will the VTC shift? d) Please explain how the resizing in b) and c) will affect the above I-V curves in each case and give an intuitive explanation of how this affects the VTC of each. Problem 2 – Inverter Delay Calculation An old implementation of MOS inverters is shown in Fig. 2a, in which a diode connected NMOS transistor is used as the load. The standard inverter implementation is shown in Fig. 2b. We are going to compare them on performance metric. Assume that both of them are driven by a standard inverter (the high input voltage is Vdd and low input voltage is 0). There is a capacitive load CL=150fF on the output node of each inverter, which is large compare to the parasitic capacitances of the devices. a) For inverter A, prove that when the output voltage characteristics satisfy the following relation: VM≈ (VOH + VOL)/2, the delay for output to rise from VOL to VM (or fall from VOH to VM) can be modeled as tp = 0.69ReqCL, even if the output swing is not rail – to – rail. Here Req is the equivalent resistance of the device driving the output, and CL is the load capacitance on the output node. b) Evaluate the propagation delays of the two inverters by measuring the delay as the time between VIN = VM and VOUT = VM. You will need to find VM, VOH and VOL for each of these two inverters first. Use the switch approximation analysis of the MOS transistor presented in class (Req = (RM + RVOH) / 2) to estimate tpLH, and same for tpHL. c) Verify tpLH and tpHL using HSPICE. (Note that there may be slight difference between your SPCE and hand calculation results, because approximations are used in our hand analysis. You can think about the reason for the discrepancy while you are not required to do so in this homework.) d) Explain why M2 is sized to be much smaller than M1 in the first (all-NMOS) circuit? Briefly comment on that. What disadvantages on performance does the inverter with NMOS-load have compared to the CMOS inverter? Left: Figure 2a: inverter A, Right: Figure 2b: Inverter B Use the following parameters: NMOS: VT0=0.6V, k’=20µA/V2, γ=0.5V1/2, λ=0.05V-1; PMOS: VT0=-0.6V, k’=7µA/V2, γ=0.5V1/2, λ=0.1V-1Problem 3 – Computing the MOSFET Capacitances a) It is always good to get a feel for design rules in a layout editor. Fire up Cadence Virtuoso with 0.24um technology. Place a minimum sized NMOS transistor and examine the dimensions. The layers are listed and shown below. Determine and list the following: a. Minimum Transistor Length b. Minimum Transistor Width c. Minimum Source/Drain Area d. Minimum Source/Drain Perimeter Please list the design rules you come across that lead to your results. (Refer to Lab2 for Cadence) b) We desire a minimum sized CMOS inverter with a symmetrical VTC (VM=VDD/2) with 0.24um technology. Calculate the following for the pull-up PMOS transistor in the design with the NMOS transistor minimum sized as in part a): a. Minimum Transistor Length b. Minimum Transistor Width c. Minimum Source/Drain Area d. Minimum Source/Drain Perimeter Assume the following: VDD = 2.5V, VM = 1.25V, and refer to Table 3.2 in the Book c) Using the same minimum size inverter from part b), determine the input capacitance (i.e. the load it presents when driven). Please calculate the capacitance during a transition. From these, determine the total load capacitance that the inverter presents. Refer to Table 3.5 for capacitor parameters. *Hint: Consider the Miller effect d) Using the g25 model provided in ‘/home/ff/ee141/MODELS/g25.mod’, please verify the accuracy of your results in part c) by determining the total input capacitance in a high-low and a low-high transition with HSPICE and comparing with your total capacitance in part c). Turn in your HSPICE input deck. You'll notice there are four corners, TT, FF, SS, FS, and SF. These represent the different variation extremes we can expect due to process variations. For example, TT stands for NMOS: typical, PMOS: typical. FS stands for NMOS: fast, PMOS: slow etc. For this homework, please use the TT model. To use these models, include the following in your HSPICE deck: .lib '/home/ff/ee141/MODELS/g25.mod' TT e) Determine VIH, VIL , NMH, and NML. *Hint: The 2 parameters r and g vary proportionally with transistor width. The equations given are derived with the minimum width in mind. (Please refer to Eq’s 5.3 and 5.10 in the book for r and
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