1EE141 – Fall 2005Lecture 17Dynamic LogicDynamic LogicAddersAddersEE141 2Announcements Project 1 due on Monday Oct 31 by 5pm• E-mail report to [email protected]• Don’t forget to attach SPICE deck Homework 7 will be posted today• Due next Thursday No labs next week2EE141 3Class Material Last lecture• PTL Today’s lecture• Dynamic Logic• AddersEE141 4Alternative Logic Styles Ratioed Logic• Reduced # of devices (reduced area)• Static power, reduced NML DCVSL• Differential outputs, reduced # of devices• Doubles the # of wires, increased Pdynamic Pass-Transistor Logic• Modular design (the same gate topology…)• Need level restoration3EE141 5Practical Guidelines Ratioed Logic, DCVSL, PTL• Reduced # of devices (area)• Difficult to design• Poor noise robustness Static CMOS• Larger area• Easy to design• Very robustUse CMOS in designs with no extreme area, speed or complexity constraintsDynamic LogicDynamic Logic4EE141 7Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDDvia a low resistance path.• fan-in of n requires 2n devices(n N-type + n P-type) Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.• Fan-in of n requires n + 2 transistors(n+1 N-type + 1 P-type)EE141 8Dynamic Gate: Basic PrincipleIn1In2PDNIn3MeMpCLKCLKOutCLOutCLKCLKABCMpMeTwo phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)5EE141 9Dynamic GateIn1In2PDNIn3MeMpCLKCLKOutCLOutCLKCLKABCMpMeTwo phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)onoff1offon((AB)+C)Out CLK A B C CLK=+⋅+⋅EE141 10Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next prechargeoperation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL6EE141 11Properties of Dynamic Gates Logic function is implemented by the PDN only•# of transistors is N + 2 (vs. 2N in static complementary CMOS) Full swing outputs (VOL= GND and VOH= VDD) Nonratioed - sizing of the devices does not affect the logic levels Faster switching speeds•reduced load capacitance due to lower input capacitance (Cin)• reduced load capacitance due to smaller output loading (Cout)• no Isc, so all the current provided by PDN goes into discharging CLEE141 12 Overall power dissipation usually higher than static CMOS• no static current path ever exists between VDDand GND (including Psc)• no glitching• higher transition probabilities• extra load on CLK PDN starts to work as soon as the input signals exceed VTn, so VM, VIHand VILequal to VTn• low noise margin (NML) Needs a precharge/evaluate clockProperties of Dynamic Gates7EE141 13Issues with Dynamic Gates Charge Leakage Charge Sharing Capacitive Coupling Clock FeedthroughEE141 14CLCLKCLKOutAMpMeLeakage sourcesCLKVOutPrechargeEvaluateDynamic Design, Issue 1: Charge Leakage8EE141 15Solution to Charge LeakageCLCLKCLKMeMpAB!OutMkpSame approach as level restorer for pass transistor logicKeeperEE141 16CLCLKCLKCACBB=0AOutMpMeCharge stored originally on CLis redistributed (shared) over CLand CAleading to reduced robustnessDynamic Design, Issue 2: Charge Sharing9EE141 17Charge Sharing ScenariosMpMeVDDφOutφAB = 0CLCaCbMaMbXCLVDDCLVoutt()CaVDDVTnVX()–()+=or∆VoutVoutt()VDD–CaCL--------VDDVTnVX()–()–==∆VoutVDDCaCaCL+----------------------–=case 1) if ∆Vout < VTncase 2) if ∆Vout > VTnEE141 18Charge Sharing ExampleCL=50fFCLKCLKA!AB!BB!BC!COutCa=15fFCc=15fFCb=15fFCd=10fFWorst-casecharge sharing:!A*B*CA*!B*C10EE141 19Solution to Charge RedistributionCLKCLKMeMpABOutMkpCLKPrecharge internal nodes using a clock-driven transistor (at the cost of increased area and power)EE141 20Dynamic Design, Issue 3: Capacitive CouplingCL1CLKCLKB=0A=0Out1MpMeOut2CL2InDynamic NAND Static NAND=1=111EE141 21Capacitive Coupling Effect-101230246Voltage (V)Time (ns)CLKInOut1Out2EE141 22Dynamic Design, Issue 4: Clock FeedthroughCLCLKCLKBAOutMpMeCoupling between Out and CLK input of the prechargedevice due to the gate to drain capacitance…So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.12EE141 23CLKCLKIn1In2In3In4OutIn &CLKOutTime (ns)Voltage (V)Clock feedthroughClock feedthroughClock Feedthrough-0.50.51.52.500.51EE141 24Other Effects Capacitive coupling (cross-talk) Substrate coupling Minority charge injection Supply noise (ground bounce)13EE141 25Cascading Dynamic GatesCLKCLKOut1InMpMeMpMeCLKCLKOut2VtCLKInOut1Out2∆VVTnOnly 0 → 1 transitions allowed at inputs!EE141 26Cascading Dynamic Gates Domino Logic np-CMOS14EE141 27Domino LogicIn1In2PDNIn3MeMpCLKCLKOut1In4PDNIn5MeMpCLKCLKOut2Mkp1 → 00 → 01 → 10 → 1Evaluation (conditional discharge)ONLY 0→1 transitions during evaluation!EE141 28Why Domino?In1CLKCLKIniPDNInjIniInjPDNIniPDNInjIniPDNInjLike falling dominos!15EE141 29Properties of Domino Logic Only non-inverting logic can be implemented Very high speed• static inverter can be skewed, only L-H transition• Input capacitance reduced – smaller logical effortEE141 30Designing with Domino LogicMpMeVDDPDNφIn1In2In3Out1φMpMeVDDPDNφIn4φOut2MrVDDInputs = 0during prechargeCan be eliminated!16EE141 31Footless DominoMpVDDCLKOut1In2 In1 1- >01-> 00->1MpVDDCLKOut20- >1In3 1->0MpVDDCLKOutnInn 1-> 00->1The first gate in the chain needs a foot switchPrecharge is rippling (next stage has to wait for propagation delay of inverter from the previous stage)Static power consumptionEE141 32Differential (Dual Rail) DominoABMeMpCLKCLK!Out = !(AB)!A !BMkpCLKOut = ABMkpMpSolves the problem of non-inverting logic1 0 1 0onoff17EE141 33np-CMOSIn1In2PDNIn3MeMpCLKCLKOut1In4PUNIn5MeMp!CLK!CLKOut2(to PDN)1 → 11 → 00 → 00 → 1Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUNEE141 34NORA LogicIn1In2PDNIn3MeMpCLKCLKOut1In4PUNIn5MeMp!CLK!CLKOut2(to PDN)1 → 11 → 00 → 00 → 1to otherPDN’sto otherPUN’sWARNING: Very sensitive to noise!P-blocks are slower18EE141 35Choosing a Logic Style: No Style Fits all Needs General design Considerations• Robustness (Static CMOS, Ratioed Logic)• Area (Pseudo-NMOS, Static CMOS)• Speed (Dynamic,
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