EE1411EECS1411Lecture #17EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 17Lecture 17CMOS ScalingCMOS ScalingEE1412EECS1412Lecture #17AnnouncementsAnnouncements Homework #7 due today Project #1 out today, due next Thurs. Midterm 2: Thurs. Nov. 5th, 6:30-8:00pm, room TBAEE1413EECS1413Lecture #17CMOS Transistor CMOS Transistor ScalingScalingEE1414EECS1414Lecture #17Goals of Technology ScalingGoals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Or build same products cheaper Price of a transistor has to be reduced But also want to be faster, smaller, lower power…EE1415EECS1415Lecture #17Technology ScalingTechnology Scaling Benefits of 30% “Dennard” scaling (1974): Double transistor density Reduce gate delay by 30% (increase operating frequency by 43%) Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency) Die size used to increase by 14% per generation (not any more) Technology generation spans 2-3 yearsEE1416EECS1416Lecture #17Technology Scaling Models Technology Scaling Models • Full Scaling (Constant Electrical Field)• Fixed Voltage Scaling• General Scalingideal model — dimensions and voltages scaletogether by the same factor Smost common model until 1990’sonly dimensions scale, voltages remain constantmost realistic for today’s situation —voltages and dimensions scale with different factorsEE1417EECS1417Lecture #17ScalingScalingLxLDL/Sx/SLD/SLWL/SW/SEE1418EECS1418Lecture #17Full Scaling (Full Scaling (DennardDennard, Long, Long--Channel)Channel) W, L, tox: 1/S VDD, VT: 1/S Area: WL Cox: 1/tox CL: CoxWL ID: Cox(W/L)(VDD-VT)2 Req: VDD/IDSATEE1419EECS1419Lecture #17Full Scaling (Full Scaling (DennardDennard, Long, Long--Channel)Channel) W, L, tox: 1/S VDD, VT: 1/S tp: ReqCL Pavg: CLVDD2/tp Pavg/A: CoxVDD2/tpEE14110EECS14110Lecture #17Scaling Relationships for Long Channel DevicesScaling Relationships for Long Channel DevicesEE14111EECS14111Lecture #17Full Scaling (Full Scaling (DennardDennard, Short, Short--Channel)Channel) W, L, tox: 1/S VDD, VT: 1/S Area: WL Cox: 1/tox CL: CoxWL ID: WCoxvsat(VDD-VT)2/(VDD-VT-EcritL) Req: VDD/IDSATEE14112EECS14112Lecture #17Full Scaling (Full Scaling (DennardDennard, Short, Short--Channel)Channel) W, L, tox: 1/S VDD, VT: 1/S tp: ReqCL Pavg: CLVDD2/tp Pavg/A: CoxVDD2/tpEE14113EECS14113Lecture #17Transistor ScalingTransistor Scaling(Velocity(Velocity--Saturated Devices)Saturated Devices)EE14114EECS14114Lecture #17Interconnect ScalingInterconnect ScalingEE14115EECS14115Lecture #17Interconnect Length DistributionInterconnect Length DistributionFrom Magen et al., “Interconnect Power Dissipation in a Microprocessor”SLocal= STechnologySGlobal= SDieEE14116EECS14116Lecture #17Resistance Scaling (local)Resistance Scaling (local)WLHScale W, H, and L:Rw= ρL/(WH)Rwα (1/S) / [(1/S) (1/S)]ÆRwα S(R/□αS)EE14117EECS14117Lecture #17Resistance Scaling (global)Resistance Scaling (global)WLHScale W, H, constant L:Rw= ρL/(WH)Rwα 1/[(1/S) (1/S)]Æ Rwα S2EE14118EECS14118Lecture #17Wire Scaling (Scenario 1)Wire Scaling (Scenario 1)Cppα WL/H Cpp’ α 1/SCfringeα ~L Cfringe’ α 1/SRwα L/(WT) Rw’ α Stpwireα RwCwtpwire’ const.Bad news: gates speed up by S…EE14119EECS14119Lecture #17Wire Scaling (Scenario 2)Wire Scaling (Scenario 2)Cppα WL/H Cpp’ α 1/SCfringeα ~L Cfringe’ α 1/SRwα L/(WT) Rw’const.tpwireα RwCwtpwire’ α 1/SBetter (wire RC tracks inverters), but…EE14120EECS14120Lecture #17Scenario 2: Scenario 2: IntralayerIntralayerCapacitanceCapacitanceCpp,sideα LT/D Cpp,side’ const.•Cpp,side/Length increasesÆ Crosstalk, coupling issues get worse• Aspect ratio limited – eventually have to scale T• Different metal layers have different TWLDW/SL/SD/SEE14121EECS14121Lecture #17Wire Scaling (Scenario 2, Global)Wire Scaling (Scenario 2, Global)Cppα WL/H Cpp’constCfringeα ~L Cfringe’ ~constRwα L/(WT) Rw’ α Stpwireα RwCwtpwire’ α SVery bad: wire delay S2 worse than gatesEE14122EECS14122Lecture #17Modern InterconnectModern Interconnect 90nm processEE14123EECS14123Lecture #17Next LectureNext Lecture Ratioed and Pass Transistor
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