DOC PREVIEW
Berkeley ELENG 141 - Performance Power

This preview shows page 1-2-3 out of 8 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 8 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 8 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 8 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 8 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

1EE1411EE141 – S04Performance (cntd)PowerEE141EE141--Spring 2004Spring 2004Lecture 7Lecture 7EE1412EE141 – S04Important!Important! Lab 3 this weekEE1413EE141 – S04Today’s lectureToday’s lecture Inverter Performance Optimization  Power dissipationEE1414EE141 – S04MOS CapacitancesMOS CapacitancesDynamic BehaviorDynamic Behavior2EE1415EE141 – S040 0.5 1 1.5 2 2.5x 10-10-0.500.511.522.53t (sec)Vout(V)Transient ResponseTransient Responsetp= 0.69 CL(Reqn+Reqp)/2?tpLHtpHLEE1416EE141 – S04Design for PerformanceDesign for Performance Keep capacitances small Increase transistor sizes watch out for self-loading! Increase VDD(?)EE1417EE141 – S04Delay as a function of VDelay as a function of VDDDD0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.411.522.533.544.555.5VDD(V)tp(normalized)EE1418EE141 – S042 4 6 8 10 12 1422.22.42.62.833.23.43.63.8x 10-11Stp(sec)Device SizingDevice Sizing(for fixed load)Self-loading effect:Intrinsic capacitancesdominate3EE1419EE141 – S041 1.5 2 2.5 3 3.5 4 4.5 533.544.55x 10-11βtp(sec)NMOS/PMOS ratioNMOS/PMOS ratiotpLHtpHLtpβ = Wp/WnEE14110EE141 – S04Impact of Rise Time on DelayImpact of Rise Time on DelaytpHL(nsec)0.350.30.250.20.15trise (nsec)10.80.60.40.20tp= tstep(i)+ ηtstep(i-1)EE14111EE141 – S04Power DissipationPower DissipationEE14112EE141 – S04Where Does Power Go in CMOS?Where Does Power Go in CMOS?• Dynamic Power Consumption• Short Circuit Currents• LeakageCharging and Discharging CapacitorsShort Circuit Path between Supply Rails during SwitchingLeaking diodes and transistors4EE14113EE141 – S04Dynamic Power DissipationDynamic Power DissipationEnergy/transition = CL * Vdd2Power = Energy/transition * f = CL* Vdd2* fNeed to reduce CL, Vdd, and f to reduce power.Vin VoutCLVddNot a function of transistor sizes!EE14114EE141 – S04Modification for Circuits with Reduced SwingCLVddVddVdd -VtE01→CLVddVddVt–()••=Can exploit reduced swing to lower power(e.g., reduced bit-line swing in memory)EE14115EE141 – S04Adiabatic Charging222EE14116EE141 – S04Adiabatic Charging5EE14117EE141 – S04Node Transition Activity and PowerNode Transition Activity and PowerConsider switching a CMOS gate for N clock cyclesENCLVdd•2nN()•=n(N): the number of 0->1 transition in N clock cyclesEN : the energy consumed for N clock cyclesPavgN∞→limENN---- ---- fclk•=nN()N----- --- ----N∞→lim⎝⎠⎛⎞C•LVdd•2fclk•=α01→nN()N----- -------N∞→lim=Pavg=α01→C•LVdd•2fclk•EE14118EE141 – S04Short Circuit CurrentsVin VoutCLVddIVDD (mA)0.150.100.05Vin (V)5.04.03.02.01.00.0EE14119EE141 – S04How to keep Short-Circuit Currents Down?Short circuit current goes to zero if tfall>> trise,but can’t do this for cascade logic, so ...EE14120EE141 – S04Minimizing Short-Circuit Power0 1 2 3 4 5012345678tsin/tsoutPnormVdd =1.5Vdd =2.5Vdd =3.36EE14121EE141 – S04LeakageVoutVddSub-ThresholdCurrentDrain JunctionLeakageSub-threshold current one of most compelling issuesin low-energy circuit design!EE14122EE141 – S04Reverse-Biased Diode LeakageNp+p+Reverse Leakage Current+-VddGATEIDL = JS × AJS = 10-100 pA/µm2 at 25 deg C for 0.25µm CMOSJS doubles for every 9 deg C!EE14123EE141 – S04The SubThe Sub--Micron MOS TransistorMicron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic ResistancesEE14124EE141 – S04Threshold VariationsThreshold VariationsVTLLong-channel thresholdLow VDSthresholdThreshold as a function of the length (for low VDS) Drain-induced barrier lowering (for low L)VDSVT7EE14125EE141 – S04SubSub--Threshold ConductionThreshold Conduction0 0.5 1 1.5 2 2.510-1210-1010-810-610-410-2VGS(V)ID(A)VTLinearExponentialQuadraticTypical values for S:60 .. 100 mV/decadeThe Slope FactoroxDnkTqVDCCneIIGS+= 1 ,~0S is ∆VGSfor ID2/ID1=10EE14126EE141 – S04SubSub--Threshold Threshold IIDDvsvsVVGSGSVDSfrom 0 to 0.5V⎟⎟⎠⎞⎜⎜⎝⎛−=−kTqVnkTqVDDSGSeeII 10EE14127EE141 – S04SubSub--Threshold Threshold IIDDvsvsVVDSDS()DSkTqVnkTqVDVeeIIDSGS⋅+⎟⎟⎠⎞⎜⎜⎝⎛−=−λ110VGSfrom 0 to 0.3VEE14128EE141 – S04Subthreshold Leakage Component8EE14129EE141 – S04Static Power ConsumptionVin=5VVoutCLVddIstatPstat = P(In=1).Vdd . IstatWasted energy …Should be avoided in most cases,but could help reducing energy in others (e.g. sense amps)EE14130EE141 – S04Principles for Power ReductionPrinciples for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 … 0.9 V by 2010!) Reduce switching activity Reduce physical capacitanceEE14131EE141 – S04Next LectureNext Lecture Optimizing for Performance and


View Full Document

Berkeley ELENG 141 - Performance Power

Documents in this Course
Adders

Adders

7 pages

Memory

Memory

33 pages

I/O

I/O

14 pages

Lecture 8

Lecture 8

34 pages

Lab 3

Lab 3

2 pages

I/O

I/O

17 pages

Project

Project

6 pages

Adders

Adders

15 pages

SRAM

SRAM

13 pages

Load more
Download Performance Power
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Performance Power and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Performance Power 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?