EE1411EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsCircuitsCircuitsLecture 13Lecture 13EE141EECS1411Lecture #13Logical EffortLogical EffortAnnouncementsAnnouncements Project starts end next week New assignment posted on Mondaygp y Midterm results on WeEE141EECS1412Lecture #13EE1412Class MaterialClass Material Last lecture Design for speed Today’s lecture Logical effort Reading (Chapter 6)EE141EECS1413Lecture #13Fast Complex Gates:Fast Complex Gates:Design Technique 1Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizingInNCLMNDistributed RC lineM1 > M2 > M3 > … > MN(the FET closest to theEE141EECS1414Lecture #13C3C2C1In1In2In3M1M2M3(the FET closest to theoutput is the smallest)Can reduce delay by more than 20%; Be careful: input loading, junction caps, decreasing gains as technology shrinksEE1413Fast Complex Gates:Fast Complex Gates:Design Technique 2Design Technique 2 Transistor orderingC2In2In3M2M3CLC2In2In1M2M3CLcritical path critical pathcharged1charged110→1chargeddischargedEE141EECS1415Lecture #13C1In1M1C1In3M10→1chargeddelay determined by time to discharge CL, C1and C2delay determined by time to discharge CL1dischargedFast Complex Gates:Fast Complex Gates:Design Technique 3Design Technique 3 Alternate logic structuresF = ABCDEFGHEE141EECS1416Lecture #13EE1414Logic RestructuringLogic RestructuringEE141EECS1417Lecture #13Fast Complex Gates:Fast Complex Gates:Design Technique 4Design Technique 4 Reducing the voltage swing linear reduction in delay also reduces power consumptionBtth fll i t i l !tpHL= 0.5 (CL VDD) / IDSATn= 0.5 (CL Vswing) / IDSATnEE141EECS1418Lecture #13But the following gate is slower! May require use of “sense amplifiers” on the receiving end to restore the signal level (memory design)EE1415Fast Complex Gates:Fast Complex Gates:Design Technique 5Design Technique 5 Isolating fan-in from fan-out using buffer itiinsertionCLCLEE141EECS1419Lecture #13 How to decide if this the right thing to do? Logical effort Extension of buffer sizing problemLogical Logical EffortEffortEE141EECS14110Lecture #13EE1416Buffer ExampleBuffer ExampleIn Out()1Ninv iiDelay t fγ==+∑CL = CN+112 Nf=C/CC1C2CNEE141EECS14111Lecture #13For given N: Ci+1/Ci= Ci/Ci-1To find N: Ci+1/Ci~ 4How to generalize this to any logic path?fi= Ci+1/CiDelay Optimization ExampleDelay Optimization ExampleCin j+3 Delay of NAND gate:(),, , ,1 , ,,,123234pj sqn nj D inj inj G njnjin jjGLtR WCC C CWWCtRCLγ++=+=⎛⎞=+⎜⎟⎜⎟Cin,j+3EE141EECS14112Lecture #13,,,,1,,42pjsq nGin jin jp j nand nandin jtRCLCCttCγγ++⎜⎟⎜⎟⎝⎠⎛⎞=+⎜⎟⎜⎟⎝⎠EE1417Delay Optimization ExampleDelay Optimization ExampleCin j+3 Delay of NOR gate:(),2 , ,2 ,3 ,2 ,2,2,326565pj sqn nj D inj inj G njnjin jjGLtR WCC C CWWCtRCLγ++++++++=+=⎛⎞=+⎜⎟⎜⎟Cin,j+3EE141EECS14113Lecture #13,2,,2,3,2,255pjsq nGin jin jp j nor norin jtRCLCCttCγγ++++++⎜⎟⎜⎟⎝⎠⎛⎞=+⎜⎟⎜⎟⎝⎠Delay Optimization ExampleDelay Optimization ExampleCin j+3 Total delay is:,1 ,2 ,3,,1,2in j in j in jpnand nand inv inv nor norin j in j in jCCCtt t tCCCγγγ+++++⎛⎞⎛⎞⎛⎞=+++++⎜⎟⎜⎟⎜⎟⎜⎟⎜⎟⎜⎟⎝⎠⎝⎠⎝⎠Cin,j+3Normalized tot:EE141EECS14114Lecture #1312312pj j jnand inv nornand inv norinv inv j inv j inv jtC C CtttttC tC tCγγγ+++++⎛⎞⎛⎞⎛⎞=+++++⎜⎟⎜⎟⎜⎟⎜⎟⎜⎟⎜⎟⎝⎠⎝⎠⎝⎠Normalized to tinv:EE1418Logical EffortLogical EffortLinv ginCDelay k tCγ⎛⎞=⋅ +⎜⎟⎝⎠()ininvtpLEf⎝⎠=+⋅Measure everything in units of tinv(divide by tinv):p – intrinsic delay (kγg) - gate parameter ≠ f(W)LE – logical effort (k) – gate parameter ≠ f(W)f–electrical effort (effective fanout)EE141EECS14115Lecture #13felectrical effort (effective fanout)Normalize everything to an inverter:LEinv=1, pinv= γDelay in a Logic GateDelay in a Logic GateGate delay:yDelay = EF + p (measured in units of tinv)effective fanoutintrinsic delayEffective fanout:EF = LE fEE141EECS14116Lecture #13logical effortelectrical fanout = Cout/CinLogical effort is a function of topology, independent of sizingEffective fanout is a function of load/gate sizeEE1419Logical EffortLogical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS gatesintrinsic delay of all static CMOS gates Logical effort LE is defined as: (Req,gateCin,gate)/(Req,invCin,inv) Easiest way to calculate (usually): – Size gate to deliver same current as an inverter, take ti f t i t it t i t itEE141EECS14117Lecture #13ratio of gate input capacitance to inverter capacitance LE increases with gate complexityLogical EffortLogical EffortCalculating LE by sizing for same drive strength:VVVBAFVDDVDDABAFVDDAAF1222244EE141EECS14118Lecture #13LE = 1LE = LE = ABB211Inverter 2-input NAND 2-input NOREE14110Logical EffortLogical EffortCalculating LE by sizing for same drive strength:VVVBAFVDDVDDABAFVDDAAF1222244EE141EECS14119Lecture #13LE = 1LE = 4/3LE = 5/3ABB211Inverter 2-input NAND 2-input NORLogical Effort of GatesLogical Effort of Gates)tNANDNormalized delay (d)tpINVtpNANDLE=p=d=LE=p=d=EE141EECS14120Lecture #13Fan-out (f)1 2 3 4 5 6 7 p = γ·Fan-in(for top input)EE14111Logical Effort of GatesLogical Effort of Gates)tNANDNormalized delay (d)tpINVtpNANDLE=1p=γd=f+γLE=4/3p=2γd=(4/3)f+2γEE141EECS14121Lecture #13Fan-out (f)1 2 3 4 5 6 7 p = γ·Fan-in(for top input)Logical Effort of GatesLogical Effort of Gates/3;p = 2EffortDelay2345Inverter:g = 1;p = 12-input NAND:g = 4/3Normalized DelayEffective FanoutEE141EECS14122Lecture #13IntrinsicDelay12345Fanout f1EE14112Add Branching EffortAdd Branching EffortBranching effort:Branching effort: ,,,L on path L off pathLon pathCCbC−−−+=CL,onpathEE141EECS14123Lecture #13CL,off_pathMultistage NetworksMultistage Networks()NiiiDelaypLEf=+⋅∑Effective fanout: EFi= LEifiPath electrical fanout: F = Cout/CinPath logical effort: ΠLE = LE1LE2…LEN()1iiiiyp f=∑EE141EECS14124Lecture #13Branching effort: ΠB = b1b2…bNPath effort: PE = ΠLE ΠΒ FPath delay D = Σdi= Σpi+ ΣEFiEE14113Optimum Effort per StageOptimum Effort per StageWhen each stage bears the same effort:NEF PE=NEFPE=Minimum path delayEffective fanouts: LE1f1= LE2f2= … = LENfNEE141EECS14125Lecture #13()1/11ˆNNNii i iiiDLEfpNPE p===+=⋅+∑∑Minimum path delayOptimal Number of
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