Borivoje Nikolic Lab #5: Switch Level Simulation EECS 141CINABAUNIVERSITY OF CALIFORNIACollege of EngineeringDepartment of Electrical Engineering and Computer SciencesLast modified on September 14, 2003 by Liang Teck Pang ([email protected])Borivoje Nikolic Lab #5: Switch Level Simulation EECS 1411. ObjectiveThis week you will be working extensively with IRSIM, the switch level simulator. You will find this lab particularly important for your project, because it demonstrates one of the fastest ways to verify that your logic designs work. 2. Background: Using IRSIMThe IRSIM switch level simulator gives you access to a powerful tool for rapidly verifying that your circuitdesigns are functionally correct. In Lab 4, you learnt how to extract circuit netlists from Cadence. You learnt to extract a HSPICE netlist andconvert it to a SIM format that can be used with IRSIM. We will now reuse the inverter.sim netlist obtainedfrom Lab4 and run a functional simulation in IRSIM.Information on IRSIM can be found in http://bwrc.eecs.berkeley.edu/Classes/icbook/IRSIM/irsim.pdfAlso, you can type man irsim at the UNIX prompt to get the manual pages of irsim. Finally, in IRSIM, you can type help or help <command> to get information on the IRSIM commands.a. Type the following command to convert hspice netlist to the sim format. /usr/xpg4/bin/awk –f hspice2sim -v "l=0.12" "n=TSMC25DN" "p=TSMC25DP" inverter.hsp >! inverter.sim b. Run IRSIM with the following command/share/b/bin/irsim /share/b/cad/src/irsim/test-input/scmos60.prm inverter.simThis calls up IRSIM and load in the parameter file and the netlist. The parameter file used here is for an older technology and thus timing information will not be accurate.a. Run the waveform analyzer and put all the nets in the analyzer using the following commandsirsim> ana in out vdd gndThe values of vdd and gnd are automatically given as 1 and 0 respectively. Advance by a time stepand check that all the signals have the right values. irsim> sSet the value of in to 1, advance by a time step, then set it to zero. Observe the waveform for out. irsim> h inirsim> sirsim> l inirsim> sb. If you want to save your results from IRSIM, click on “print/file”. It will then prompt you to enter a name for the postscript file it will save to. To print, copy the file from your UNIX directory to the local machine using SSH Secure File Transfer, open in GSview, and print.3. Tasksa. Complete the truth tables for the following schematics. For your convenience the blank truth tables are provided on the following page. Go from left to right, top to bottom.Circuit 1 (Top Left)GEN CIN PROP COUTINV0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Circuit 2 (Top Right)GENINV CININV PROPINV COUT0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Circuit 3 (Center Left)CIN PROP PROPINV CININV SUM0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1Circuit 4 (Center Right)A B GENINV GEN0 00 11 01 1Circuit 6 (Bottom Center)A AINV01Circuit 7 (Bottom Right)B BINV01Circuit 5 (Bottom Left)A AINV B BINV PROP0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1c. Why do you think this adder generates both an output signal and its complements? What are some of the advantages and disadvantages of this technique?d. Open up Cadence and draw out the schematics. The result should be ONE circuit with inputs A, B, CIN, CININV and outputs SUM, COUT, COUTINV.e. Create a sim netlist. (NOTE: Use the “hierarchical” netlist option in Cadence to preserve the device and node names). Launch IRSIM and using this derive a truth table for the adder. (Generate all the possible input combinations and read the outputs). DO NOT assume that CININV is the complement of CIN. Why do the outputs become undefined (filled with cross hatches) during part of the transitions? Observe the outputs and intermediate signals; are they what you expected? What happened when CIN and CININV had the same value? Would this ever happen in a real life application of this circuit?f. Your lab ends here. For your project, you would continue the design flow by generating a layoutfor the circuit in the same manner done in the max tutorial, connecting all the fly-lines, and performing a cross probe between the layout and schematics to verify the validity of the layout.4. What To Turn Ina. The completed truth tables from above.b. The answers to the questions presented above.c. Printouts verifying that your IRSIM simulations are (in)valid. Use as little paper as possible, butmake sure the plots are
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