EE1411Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonEECS141EECS141Spring 2003Spring 2003Inverter:Inverter:Dynamic BehaviorDynamic BehaviorDejan MarkovicDiscussion 3Feb 12, 2003Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonAgendaAgenda Delay Calculation Inverter Capacitance Calculation Voltage Transfer Characteristic Layout Issues (Lab 3)EE1412Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonPropagation DelayPropagation DelayAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonWhat is a Transistor?What is a Transistor?VGS ≥ VTRonSDA Switch!|VGS|An MOS TransistorEE1413Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonThe Transistor as a SwitchThe Transistor as a SwitchVGS ≥ VTRonSDIDVDSVGS = VDDVDD/2 VDDR0RmidAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonThe CMOS Inverter: A First GlanceThe CMOS Inverter: A First GlanceVinVoutCLVDDEE1414Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonCMOS Inverter: Transient ResponseCMOS Inverter: Transient ResponsetpHL= f(Ron.CL)= 0.69 RonCLVoutVoutRnRpVDDVDDVin5VDDVin50(a) Low-to-high (b) High-to-lowCLCLAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonCMOS Inverter Propagation DelayCMOS Inverter Propagation DelayApproach 1Approach 1VDDVoutVin = VDDCLIavtpHL = CL Vswing/2IavCLkn VDD~EE1415Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonCMOS Inverter Propagation DelayCMOS Inverter Propagation DelayApproach 2Approach 2VDDVoutVin = VDDRonCLtpHL = f(Ron.CL)= 0.69 RonCLtVoutVDDRonCL10.5ln(0.5)0.36Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/Pearson0 0.5 1 1.5 2 2.5x 10-10-0.500.511.522.53t (sec)Vout(V)Transient ResponseTransient Responsetp= 0.69 CL(Reqn+Reqp)/2?tpLHtpHLEE1416Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonInverterInverterCapacitancesCapacitancesAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonThe MOS TransistorThe MOS TransistorPolysiliconAluminumEE1417Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonThe Gate CapacitanceThe Gate Capacitancetoxn+n+Cross sectionLGate oxidexdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonGateGate--toto--channel Capacitancechannel CapacitanceSDGCGCSDGCGCSDGCGCCut-offResistive SaturationMost important regions in digital design: saturation and cut-offCoxWL CoxWL (2/3)CoxWLCGC= CGCB+CGCS+CGCD[See Table 3-4 in the textbook, pg.109]EE1418Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonJunction (Diffusion) CapacitanceJunction (Diffusion) CapacitanceBottomSide wallSide wallChannelSourceNDChannel-stop implantNA+Substrate NAWxjLSAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonCapacitive Device ModelCapacitive Device ModelDSBCGDCGSCSBCDBCGBCGS = CGCS + CGSOCGD = CGCD + CGDOCGB = CGCBGEE1419Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonThe CMOS Inverter: CThe CMOS Inverter: CininCgdCgsCgsSGDSVoutVinCinCLAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonMiller EffectMiller EffectVoutVinZLZFAi1AVoutVini1Z1Z2ZLi1 =Vin (1-A)ZFi1 =VinZ1EE14110Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonMiller EffectMiller EffectZFAAZ1Z2Z1 =ZF1-AZ2 =ZF1A1 -Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonCMOS Inverter Example: CCMOS Inverter Example: CininCgdCgspCgsnCinA = -1Cgs = Cgsn + CgspCgd = Cgdn + CgdpCin= Cgs+ Cgd(1-A)+∆V-∆VEE14111Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonSummary Summary ––Things to ConsiderThings to Consider Consider all C components[also MOSFET operation region] Capacitive Device Model [Use data from Table 3-4] Miller EffectAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonVoltage TransferVoltage TransferCharacteristicCharacteristicEE14112Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonPMOS Load LinesPMOS Load LinesVDSpIDpVGSp=-2.5VGSp=-1VDSpIDnVin=0Vin=1.5VoutIDnVin=0Vin=1.5Vin= VDD+VGSpIDn= - IDpVout= VDD+VDSpVoutIDnVin= VDD+VGSpIDn= - IDpVout= VDD+VDSpAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonCMOS Inverter Load CharacteristicsCMOS Inverter Load CharacteristicsIDnVoutVin = 2.5Vin = 2Vin = 1.5Vin = 0Vin = 0.5Vin = 1NMOSVin = 0Vin = 0.5Vin = 1Vin = 1.5Vin = 2Vin = 2.5Vin = 1Vin = 1.5PMOSEE14113Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonImpact of Process VariationsImpact of Process Variations0 0.5 1 1.5 2 2.500.511.522.5Vin(V)Vout(V)Good PMOSBad NMOSGood NMOSBad PMOSNominalAdapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonLayout IssuesLayout Issues(Lab 3)(Lab 3)EE14114Adapted from “Digital Integrated Circuits2ndEd”, J.M.Rabaey, A.Chandrakasan, B.Nikolic, © 2003 Prentice Hall/PearsonTransistor LayoutTransistor Layouttoxn+n+Cross sectionLGate oxidexdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WAdapted from “Digital Integrated
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