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Berkeley ELENG 141 - Lecture 24 Timing Clock Distribution

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EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 24Lecture 24TimingTimingClock DistributionClock DistributionEE1412EECS141AnnouncementsAnnouncements Homework 8 due today Project phase three in lab this week Project reports due on Monday Poster presentations next weekEE1413EECS141Class MaterialClass Material Last lecture Multivibrators Timing Today’s lecture Finish timing Clock distribution Reading Chapter 10EE14119EECS141Clock Clock DistributionDistributionEE14120EECS141Clock DistributionClock DistributionCLKClock is distributed in a tree-like fashionH-treeEE14121EECS141More realistic HMore realistic H--treetree[Restle98]EE1412EE14122EECS141The Grid SystemThe Grid SystemDriverDriverDri v e rDri v e rGCLKGCLKGCLKGCLK•No rc-matching•Large powerEE14123EECS141Example: DEC Alpha 21164Example: DEC Alpha 21164Clock Frequency: 300 MHz - 9.3 Million TransistorsTotal Clock Load: 3.75 nFPower in Clock Distribution network : 20 W (out of 50)Uses Two Level Clock Distribution:• Single 6-stage driver at center of chip• Secondary buffers drive left and right sideclock grid in Metal3 and Metal4Total driver size: 58 cm!EE14124EECS14121164 Clocking21164 Clocking 2 phase single wire clock, distributed globally 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variationtrise= 0.35nstskew= 150pstcycle= 3.3nsClock waveformLocation of clockdriver on diepre-driverfinal driversEE14125EECS141Clock DriversEE14126EECS141Clock Skew in Alpha ProcessorClock Skew in Alpha ProcessorEE14127EECS141 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width Local clocks can be gated “off” to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checkingtrise= 0.35ns tskew= 50pstcycle= 1.67nsEV6 (Alpha 21264) ClockingEV6 (Alpha 21264) Clocking600 MHz 600 MHz ––0.35 micron CMOS0.35 micron CMOSGlobal clock waveformPLLEE1413EE14128EECS14121264 Clocking21264 ClockingEE14129EECS141EV6 Clock ResultsEV6 Clock ResultsGCLK Skew(at Vdd/2 Crossings)ps5101520253035404550ps300305310315320325330335340345GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)EE14130EECS141EV7 Clock HierarchyEV7 Clock HierarchyGCLK(CPU Core)L2L_CLK(L2 Cache)L2R_CLK(L2 Cache)NCLK(Mem Ctrl)DLLPLLSYSCLKDLLDLL+ widely dispersed drivers+ DLLs compensate static and low-frequency variation+ divides design and verification effort- DLL design and verification is added work+ tailored clocksActive Skew Management and Multiple Clock DomainsEE14131EECS141Clock AnimationsClock Animations By Phillip Restle (IBM)http://www.research.ibm.com/people/r/restle/Animations/DAC01top.htmlEE14132EECS141Next LectureNext Lecture Power distribution,


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Berkeley ELENG 141 - Lecture 24 Timing Clock Distribution

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