UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on October 27, 2008. Elad Alon FALL 2008 TERM PROJECT PHASE I EECS 141 1. Design of a 32x64-bit SRAM– Background Memory arrays are an essential building block of all digital systems. In this semester’s project, we will design an SRAM array that contains 32 64-bit words. In order to support operation as a FIFO, the memory is addressed by a 5-bit address (whose decimal value ranges from 0 to 31) that is added or subtracted to a 2-bit, 2’s complement offset (whose decimal value ranges from -2 to 1). 1.1. High level structure A block diagram of the SRAM you will be designing is shown in DECODERoff1:0ENoffb1:0Figure 1. DECODER1:01:0Figure 1. SRAM block diagram. There are three major blocks to be designed:• Binary Adder/Subtractor: This block adds a 5 bit relative address addr4:0 a 2 bit, 2’s complement offset address off1:0 to calculate the effective address a4:0. • Address decoder: The address decoder takes in the 5 address lines a4:0 produced by the adder/subtractor, and decodes them to generate 32 wordlines wl31:0 for the SRAM array. • SRAM array: Consists of an array of 32 x 64 bit SRAM cells. In addition to these blocks, the array also contains circuitry that allows data to be written into the array, and for precharging the bitlines to VDD before the read operation; these circuits are not shown in figure.2. Implementation and Constraints The goal of this project is to design a functional, compact, fast, energy-efficient SRAM for use in a high-performance or mobile microprocessor. The project will be completed in THREE phases by teams of two students. The first two phases of the project will consist of well-defined tasks (similar to the homeworks), while the final (longest) phase of the project will be much more open-ended. PHASE 1: Cell Characterization and Decoder Design (due Thursday, Oct. 30, at 5pm) Cell Characterization: In the first phase of the project, you are provided with a pre-designed SRAM cell. Characterize the cell stability by using Cadence to obtain an extracted netlist and HSPICE to perform simulations to get the read and write margins. To obtain the SRAM cell: - In Cadence, create a library “sram” linked to the gpdk090 90nm technology (see lab 2). - Create a layout cellview “sram_cell”. Do not close the cellview. - Create a schematic cellview “sram_cell”. Do not close the cellview. - Create a symbol cellview “sram_cell”. Do not close the cellview. - Now in an x-terminal, go to the directory ~/ee141/sram/sram_cell/ (this assumes that the cellviews you just created are in ~/ee141/sram/sram_cell) and type the following commands: cp –R ~ee141/fall08/project/sram_cell/schematic/ . cp –R ~ee141/fall08/project/sram_cell/layout/ . cp –R ~ee141/fall08/project/sram_cell/symbol/ . Reply “y” to all “overwrite” prompts. - Go back to Cadence and close all open cellviews. Now reopen the symbol, schematic and layout views of sram_cell. You should see the SRAM cell design. Figure 2. SRAM Read Static Noise Margin. Recalling that the wordline and bitlines are held at VDD during a read, Figure 2 shows how to extract the read static noise margin (SNM) of the cell. First, the feedback from the cross coupled inverters is broken. Next, the VTC of the “inverter” formed by half of the SRAM cell is found by sweeping V1 (the inverter’s input) from 0 to VDD and measuring V2 (the inverter’s output). This plot is then used to construct the “butterfly plot” that is V1V2WLBLBLBrepresentative of the two halves of the cell driving each other. The read SNM is the side length of the maximum possible square that can fit inside of the butterfly plot. You do not have to calculate the size of this maximum square, but you should submit the butterfly plot (generated using HSPICE) that graphically indicates the SNM. You should also measure the worst-case voltage rise in the SRAM cell during a read (i.e., the value of V2 when V1 is at VDD) and provide that value in your report. Figure 3. Write Noise Margin. During a write, VDD is applied to the worldine, and the value to be written into the memory cell is driven onto the bitlines. Thus, Figure 3 shows how to extract the write noise margin (WNM) of the cell. Again, the feedback from the cross coupled inverters is broken, and the VTC of the “inverters” are measured. Note however that in this case, the VTCs of the two halves of the SRAM are no longer the same (since one of the bitlines is driven to 0V, and the other to VDD). These VTCs are used to create a butterfly plot, and the WNM is the side length of the largest square that can fit inside of the butterfly plot. You do not have to calculate the WNM, but you should generate the butterfly plot (again using HSPICE) and graphically indicate the WNM. You should however measure the worst-case cell voltage during a write (which is found from measuring V1 when V2 is at 0V). Layout of SRAM Array: Figure 4. Arraying Procedure Figure 4 shows how the provided SRAM cell can be arrayed to minimize area. Each adjacent cell is flipped across the X or Y axis. For phase 1 of the project, you will need to V2V1V1V2array one row of SRAM cells and use the extracted layout to estimate the capacitive loading on each wordline (To conduct parasitic extraction of your layout, there will be a tutorial posted under the “Projects” section on the course website). Decoder Design: Figure 5. Decoder. The next stage is to design the 5-to-32 memory decoder. In phase 1 of the project, our goal will be to minimize the delay of the decoder from the address inputs transitioning to the wordline rising. The decoding is performed in two phases: predecoding of 3 or 2 input bits, and then final decoding of 2 bits. The enable signal EN is active high and enables the decoder outputs – this is required in order to be able to precharge the bitlines once a read or write has been completed. For phase 1, you can assume that the EN signal will go high at the same time as the address inputs transition. The predecoder drives the final wordline decoders together with a wire whose length equals the height of the memory array. The logic structure and the number of logic levels in Figure 5 are not fixed – e.g., you can exchange NANDs with NORs, or add/remove inverters. You can assume that both the true and
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