1EE141 – Fall 2005Lecture 14CMOS Design CMOS Design Optimization Optimization ––Logical EffortLogical EffortEE141 2Administrative Stuff PROJECT 1 (Start early!)• You will not be able to finish in 1 week! LABS• This week: Finish any remaining SW labs• Next week: Project help in labs HOMEWORKS• Due date for Hw6 = Mon Oct 24 (EE142 Midterm)• No new homework this week2EE141 3Important Changes NEW OH• Thursday, 1-3pm• Starting this week BI-WEEKLY REVIEW• One hour sessions every other Thursday• Starts this week (Time & Location TBD)EE141 4Schedule Last lecture: • CMOS logic gates Today: • Project launch• CMOS Design optimization• Logical effort3EE141 5Switch Delay ModelAReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintNAND-2 Inverter NOR-2EE141 6Input Pattern Effects on Delay Delay is dependent on thepattern of inputs Low-to-high transition• both inputs go low− delay is 0.69 Rp/2 CL• one input goes low− delay is 0.69 RpCL High-to-low transition• both inputs go high− delay is 0.69 2RnCLCLBRnARpBRpARnCint4EE141 757B=1→0, A=176B=1, A=1→035A=B=1→050B= 0→1, A=162B=1, A=0→169A=B=0→1Delay(ps)Input DataPatternNMOS = 0.5µm/0.25 µmPMOS = 0.75µm/0.25 µmCL= 100 fFtime [ps]Voltage [V]intBVDDAM3M4ABFM2M1-0.500.511.522.530 100 200 300 400A=B=1→0B=1→0, A=1B=1, A=1→0Delay Dependence on Input PatternsEE141 8Transistor SizingCLBRnARpBRpARnCintBRpARpARnBRnCLCint222211445EE141 9OUT = D + A • (B + C)DABCDABC12224488Sizing of a Complex CMOS GateEE141 10Fan-In ConsiderationsDCBADCBACLC3C2C1Distributed RC model(Elmore delay)tpHL= 0.69 Reqn(C1+2C2+3C3+4CL)Propagation delay deteriorates rapidly as a function of fan-in –quadratically in the worst case.6EE141 11tpas a Function of Fan-Intp(ps)fan-in0250500750100012502 4 6 8 10 12 14 16tpHLquadraticlineartptpLHtp(ps)fan-in0250500750100012502 4 6 8 10 12 14 16tpHLquadraticlineartptpLHNAND2 Gates with fan-in > 4 should be avoidedEE141 12tpas a Function of Fan-Outtp(norm.)eff. fan-out2 4 6 8 10 12 14 16tpNAND2tpNOR2tpINV12345tp(norm.)eff. fan-out2 4 6 8 10 12 14 16tpNAND2tpNOR2tpINV12345 All gates have the same drive current Slope is a function of “driving strength”7EE141 13 Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CLtp= a1FI + a2FI2+ a3FOtpas a Function of Fan-In and Fan-OutEE141 14 Progressive transistor sizing• as long as fan-out capacitance dominatesInNCLC3C2C1In1In2In3M1M2M3MNDistributed RC lineM1 > M2 > M3 > … > MN(the FET closest to theoutput is the smallest)Can reduce delay by more than 20%; Be careful: input loading, junction caps, decreasing gains as technology shrinksFast Complex Gates: Design Technique 18EE141 15 Transistor orderingC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical path critical pathcharged10→1chargedcharged1delay determined by time to discharge CL, C1and C2delay determined by time to discharge CL110→1chargeddischargeddischargedFast Complex Gates: Design Technique 2EE141 16 Alternative logic structuresF = ABCDEFGHFast Complex Gates: Design Technique 39EE141 17 Isolating fan-in from fan-out using buffer insertionCLCLFast Complex Gates: Design Technique 4EE141 18 Reducing the voltage swing• linear reduction in delay• also reduces power consumption But the following gate is much slower!• can use of “sense amplifiers” on the receiving end to restore the signal level (memory design)tpHL= 0.69 (3/4 (CL VDD)/ IDSATn )= 0.69 (3/4 (CL Vswing)/ IDSATn )Fast Complex Gates: Design Technique 510Logical EffortLogical EffortEE141Chip designers face wide array of choices• What is the best circuit topology for a function?• How large should transistors be?• How many stages of logic give least delay?Logical Effort is a method to answer these Qs• Uses simple delay model• Back of the envelope calculationsWho cares about LE?• Circuit designers who waste time in simulate/tweak loop• High-speed logic designers need to know where time is going in their logic• CAD designers need to understand circuits to build better tools? ? ?IntroductionCourtesy: D. Harris, HMC11EE141 21Logical Effort Formalism (1/4)⋅+⋅=⋅+⋅⋅⋅=inoutpinoutrinsicdriveCCtCCCRDelayγγ1169.00int Gate delay we used up to now: Another way to write this formula is:+⋅=+⋅⋅⋅=inoutgateinoutgatedriveCCCCCRDelayγτγ69.0EE141 22Logical Effort Formalism (2/4)+⋅++⋅++⋅=+++++23121jjNORNORjjINVINVjjNANDNANDCCCCCCDelayγτγτγτ In this example, the total delay is:+⋅++⋅++⋅=+++++23121jjNORINVNORjjINVINVINVjjNANDINVNANDINVCCCCCCDelayγττγττγτττ Normalized to the intrinsic time constant of INV:Courtesy: B. Murmann, Stanford12EE141 23Logical Effort Formalism (3/4) Since it is hard to fit on the back of an envelope, we define new symbols:)()()(21 NORjNORINVjINVNANDjNANDPFOLEPFOLEPFOLED +⋅++⋅++⋅=+++⋅++⋅++⋅=+++++NORjjINVNORINVjjINVINVNANDjjINVNANDINVCCCCCCDelayγττγττγτττ23121LogicalEffortFanout“Electrical Effort”ParasiticDelayCourtesy: B. Murmann, StanfordEE141 24Logical Effort Formalism (4/4) More nomenclature:• Dgate= LE·FO + P = Effort Delay + Parasitic Delay Some options to find LE of a logic gate:• Set Rdriveequal, then compare Cin• Set Cinequal, then compare Rdrive• Or simply compare R and C ratio from first principles:()()INVindrivegateindriveINVgategateCRCRLE⋅⋅==ττCourtesy: B. Murmann, Stanford13EE141DEF: Logical effort is the ratio of the input capacitance to the input capacitance of an inverter delivering the same output currentCalculating Logical EffortEE141 26LE Catalog of GatesSource: “Logical Effort,”I. Sutherland, B. Sproull, D. Harris (Morgan-Kaufmann 1999)14EE14112345612345parasitic delayeffortdelayElectrical effort: FO = Cout/CinNormalized delay: D2-input NANDinverterLE = P =D =LE = P =D =4/3 1 1FO + 12(4/3)FO + 2LE and P from Simulation DataDgate= LE·FO + P = Effort Delay + Parasitic DelayEE141Estimate the frequency of an N-stage ring oscillator:Logical Effort: LE =Electrical Effort: FO =Parasitic Delay: P =Stage Delay: D =OSC
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