1EE141Design RulesCMOS InverterMOS Transistor ModelEE141- Spring 2003Lecture 4EE141Today’s lecturez Design Rulesz The CMOS inverter at a glancez An MOS transistor model for manual analysis2EE141Important!z Labs start next weekz You must show up in one of the lab sessions next weekz If you don’t show up you will be dropped from the class» Unless you let me know that you still want to be in the classz Homework 2 will be posted later today. Due next Thursday, February 6.EE141Jan M. RabaeyDesign Rules3EE1413D PerspectivePolysiliconAluminumEE141Design Rulesz Interface between designer and process engineerz Guidelines for constructing process masksz Unit dimension: Minimum line width» scalable design rules: lambda parameter» absolute dimensions (micron rules)4EE141CMOS Process LayersLayerPolysiliconMetal1Metal2Contact To PolyContact To DiffusionViaWell (p,n)Active Area (n+,p+)Color RepresentationYellowGreenRedBlueMagentaBlackBlackBlackSelect (p+,n+)GreenEE141Layers in 0.25 µm CMOS process5EE141Intra-Layer Design RulesMetal2431090 WellActive33Polysilicon22Different PotentialSame PotentialMetal1332Contactor ViaSelect2or62HoleEE141Transistor Layout1253Transistor6EE141Vias and Contacts121ViaMetal toPoly ContactMetal toActive Contact1254322EE141Select Layer133222WellSubstrateSelect357EE141CMOS Inverter LayoutAA’np-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-A’AA’EE141Layout Editor8EE141Design Rule Checkerpoly_not_fet to all_diff minimum spacing = 0.14 um.EE141Sticks Diagram13InOutVDDGNDStick diagram of inverter• Dimensionless layout entities• Only topology is important• Final layout generated by “compaction” program9EE141Jan M. RabaeyCMOS InverterMOS TransistorEE141What is a Transistor?VGS ≥ VTRonSDA Switch!|VGS|A MOS Transistor10EE141NMOS and PMOSVGS<0PMOS TransistorVGS>0NMOS TransistorSDGSDGEE141The CMOS Inverter: A First GlanceVinVoutCLVDD11EE141CMOS InverterPolysiliconInOutVDDGNDPMOS2λMetal 1NMOSOutInVDDPMOSNMOSContactsN WellEE141Two InvertersConnect in MetalShare power and groundAbut cellsVDD12EE141Switch Model of CMOS TransistorRon|VGS| < |VT||VGS| > |VT||VGS|EE141CMOS InverterFirst-Order DC AnalysisVOL= 0VOH= VDDVM= f(Rn, Rp)VDDVDDVin5VDDVin50VoutVoutRnRp13EE141CMOS Inverter: Transient ResponsetpHL= f(Ron.CL)= 0.69 RonCLVoutVoutRnRpVDDVDDVin5VDDVin50(a) Low-to-high (b) High-to-lowCLCLEE141CMOS Propertiesz Full rail-to-rail swingz Symmetrical VTCz Propagation delay function of load capacitance and resistance of transistorsz No static power dissipationz Direct path current during switching14EE141The MOS TransistorPolysiliconAluminumEE141MOS Transistors -Types and SymbolsDSGDSGGSD DSGNMOSEnhancementNMOSPMOSDepletionEnhancementBNMOS withBulk Contact15EE141Threshold Voltage: Conceptn+p-substrateDSGBVGS+–Depletionregionn-channeln+EE141The Threshold VoltageThresholdFermi potential2φFis approximately - 0.6V for p-type substratesγ –the body factorVT0is approximately 0.45V for our process16EE141The Body Effect-2.5 -2 -1.5 -1 -0.5 00.40.450.50.550.60.650.70.750.80.850.9VBS (V)VT (V)EE141The Drain CurrentCharge in the channel is controlled by the gate voltage: Drain current is proportional to charge and velocity:17EE141The Drain CurrentCombining velocity and charge:Integrating over the channel:Transconductance:EE141Transistor in Linearn+n+p-substrateDSGBVGSxLV(x)+–VDSIDMOS transistor and its bias conditionsLinear (Resistive) mode18EE141Transistor in Saturationn+n+SGVGSDVDS > VGS - VTVGS - VT+-Pinch-offEE141SaturationFor VGD< VT, the drain current saturatesIncluding channel-length modulation()22TGSnDVVLWkI −′=()()DSTGSnDVVVLWkI λ+−′= 12219EE141Modes of OperationCutoff:VGS< VTID= 0Resistive:VT< VGS ; VGS− VT> VDS()22TGSnDVVLWkI −′=Saturation:VT< VGS ; VGS− VT< VDS()⎥⎥⎦⎤⎢⎢⎣⎡−−′=222DSDSTGSnDVVVVLWkIEE141Current-Voltage RelationsA Good Ol’ TransistorQuadraticRelationship0 0.5 1 1.5 2 2.50123456x 10-4VDS(V)ID(A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistive SaturationVDS= VGS-VT20EE141A model for manual analysisEE141Current-Voltage RelationsThe Deep-Submicron EraLinearRelationship-4VDS(V)0 0.5 1 1.5 2 2.500.511.522.5x 10ID(A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VEarly Saturation21EE141Velocity Saturationξ(V/µm)ξc= 1.5υn(m/s)υsat= 105Constant mobility (slope = µ)Constant velocityEE141Velocity SaturationIDLong-channel deviceShort-channel deviceVDSVDSATVGS-VTVGS = VDD22EE141IDversus VGS0 0.5 1 1.5 2 2.50123456x 10-4VGS(V)ID(A)0 0.5 1 1.5 2 2.500.511.522.5x 10-4VGS(V)ID(A)quadraticquadraticlinearLong ChannelShort ChannelEE141IDversus VDS-4VDS(V)0 0.5 1 1.5 2 2.500.511.522.5x 10ID(A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 V0 0.5 1 1.5 2 2.50123456x 10-4VDS(V)ID(A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistive SaturationVDS= VGS-VTLong Channel Short Channel23EE141Including Velocity SaturationApproximate velocity:And integrate current again:In deep submicron, there are four regions of operation:(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturationEE141Regions of OperationLong Channel Short Channel24EE141An Unified Modelfor Manual AnalysisSDGBEE141Regions of Operation0 0.5 1 1.5 2 2.500.511.522.5x 10-4DSV(V)ID(A)VelocitySaturatedLinearSaturatedVDSAT=VGTVDS=VDSATVDS=VGT0 0.5 1 1.5 2 2.500.511.522.5x 10-4DSV(V)DSV(V)ID(A)VelocitySaturatedLinearSaturatedVDSAT=VGTVDS=VDSATVDS=VGT25EE141A PMOS Transistor-2.5 -2 -1.5 -1 -0.5 0-1-0.8-0.6-0.4-0.20x 10-4VDS(V)ID(A)Assume all variablesnegative!VGS = -1.0VVGS = -1.5VVGS = -2.0VVGS = -2.5VEE141Transistor Model for Manual Analysis26EE141The Transistor as a SwitchVGS ≥ VTRonSDIDVDSVGS = VDDVDD/2 VDDR0RmidEE141The Transistor as a Switch0.5 1 1.5 2 2.501234567x 105VDD (V)Req (Ohm)27EE141The Transistor as a SwitchEE141Future Perspectives25 nm MOS transistor (Folded
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