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Berkeley ELENG 141 - Multipliers

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EE141EE141EECS1411Lecture #20EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsLecture 28Lecture 28MultipliersMultipliersEE141EECS1412Lecture #202AnnouncementsAnnouncements Project – Phase 2 Posted Sign up for one of three project goals today Graded Phase 1 and Midterm 2 will be returned next Fr Hw Lab in week 13EE141EE141EECS1413Lecture #20Class MaterialClass Material Last lecture Power Intro to sequential Today’s lecture: Intermezzo Multipliers Reading Chapter 11EE141EECS1414Lecture #20MultipliersMultipliersEE141EE141EECS1415Lecture #20x+Partial productsMultiplicandMultiplierResult1 0 1 0 1 01 0 1 0 1 01 0 1 0 1 01 1 1 0 0 1 1 1 00 0 0 0 0 01 0 1 0 1 01 0 1 1Binary MultiplicationBinary MultiplicationEE141EECS1416Lecture #20ZX··Y×Zk2kk0=MN1–+∑==Xi2ii0=M1–∑⎝⎠⎜⎟⎜⎟⎜⎟⎛⎞Yj2jj0=N1–∑⎝⎠⎜⎟⎜⎟⎜⎟⎛⎞=XiYj2ij+j0=N1–∑⎝⎠⎜⎟⎜⎟⎜⎟⎛⎞i0=M1–∑=XXi2ii0=M1–∑=YYj2jj0=N1–∑=withBinary MultiplicationBinary MultiplicationEE141EE141EECS1417Lecture #20Y0Y1X3X2X1X0X3HAX2FAX1FAX0HAY2X3FAX2FAX1FAX0HAZ1Z3Z6Z7Z5Z4Y3X3FAX2FAX1FAX0HAZ2Z0The Array MultiplierThe Array MultiplierEE141EECS1418Lecture #20HA FA FA HAHAFAFAFAFAFA FA HACritical Path 1Critical Path 2Critical Path 1 & 2()()()12 1mult carry sum andtMNtNtt⎡⎤≈−+−⋅+−⋅+⎣⎦The MThe M--byby--N Array Multiplier: N Array Multiplier: Critical PathCritical PathEE141EE141EECS1419Lecture #20ABPCiVDDAAAVDDCiAPABVDDVDDCiCiCoSCiPPPPPSum GenerationCarry GenerationSetupTransmissionTransmission--Gate Full AdderGate Full AdderBalanced tsumand tcarryEE141EECS14110Lecture #20CarryCarry--Save MultiplierSave MultiplierHA HA HA HAFAFAFAHAFAHA FA FAFAHA FA HAVector Merging Adder()1mult and carry mergett Ntt=+−⋅ +EE141EE141EECS14111Lecture #20Multiplier FloorplanMultiplier FloorplanSCSCSCSCSCSCSCSCSCSCSCSCSCSCSCSCZ0Z1Z2Z3Z4Z5Z6Z7X0X1X2X3Y1Y2Y3Y0Vector Merging CellHA Multiplier CellFA Multiplier CellX and Y signals are broadcastedthrough the complete array.( )EE141EECS14112Lecture #20WallaceWallace--Tree MultiplierTree MultiplierFAFAFAFAy0y1y2y3y4y5SCi-1Ci-1Ci-1CiCiCiFAy0y1y2FAy3y4y5FAFACCSCi-1Ci-1Ci-1CiCiCiEE141EE141EECS14113Lecture #20WallaceWallace--Tree MultiplierTree Multiplier6543210 6543210Partial products First stageBit position6543210 6543210Second stage Final adderFA HA(a) (b)(c) (d)EE141EECS14114Lecture #20WallaceWallace--Tree MultiplierTree MultiplierPartial productsFirst stageSecond stageFinal adderFA FA FAHA HAFAx3y3z7z6z5z4z3z2z1z0x3y2x2y3x1y1x3y0x2y0x0y1x0y2x2y2x1y3x1y2x3y1x0y3x1y0x0y0x2y1HEE141EE141EECS14115Lecture #20Multipliers Multipliers ––SummarySummary Optimization constraints different than in binary adder Once again: – Need to identify critical path– And find ways to use parallelism to reduce it Other possible techniques Logarithmic versus linear (Wallace Tree Mult) Data encoding (Booth) PipeliningFirst glimpse at system level optimizationEE141EECS14116Lecture #20The Binary ShifterThe Binary ShifterAiAi-1BiBi-1RightLeftnopBit-Slice i...EE141EE141EECS14117Lecture #20The Barrel ShifterThe Barrel ShifterSh3Sh2Sh1Sh0Sh3Sh2Sh1A3A2A1A0B3B2B1B0: Control Wire: Data WireArea Dominated by WiringEE141EECS14118Lecture #204x4 Barrel Shifter4x4 Barrel ShifterBufferSh3Sh2Sh1Sh0A3A2A1A0Widthbarrel~ 2 pmMEE141EE141EECS14119Lecture #20Logarithmic ShifterLogarithmic ShifterSh1 Sh1 Sh2 Sh2 Sh4 Sh4A3A2A1A0B1B0B2B3EE141EECS14120Lecture #20A3A2A1A0Out3Out2Out1Out000--7 bit Logarithmic Shifter7 bit Logarithmic Shifter()[]()1222...2121log−+⋅=++++⋅≈−KpKpwidthKmKmEE141EE141EECS14121Lecture #20Sequential Sequential LogicLogicEE141EECS14122Lecture #20Latch versus Register (FlipLatch versus Register (Flip--flop) flop) --REVIEWREVIEWDClkQDClkQ Register: edge-triggeredstores data when clock rises Clk ClkDDQQ Latch: level-sensitiveclock is low - hold modeclock is high - transparentEE141EE141EECS14123Lecture #20Characterizing Characterizing Timing Timing --REVIEWREVIEWRegisterLatchClkDQtC → QClkDQtC → QtD →QEE141EECS14124Lecture #20Timing Timing Definitions Definitions --REVIEWREVIEWtCLKtDtc→qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQEE141EE141EECS14125Lecture #20Storage MechanismsStorage MechanismsDCLKCLKQDynamicCLKCLKCLKDQStaticEE141EECS14126Lecture #20Vi1Vo2Vo2 =Vi1Vo1=Vi2ACBPositive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1Vo1Vo1= Vi2 Vo2Vo1= Vi2 Vo2= Vi1EE141EE141EECS14127Lecture #20Gain should be larger than 1 in the transition regionACdBVi25Vo1Vi15Vo2ACdBVi25Vo1Vi15Vo2MetaMeta--StabilityStabilityEE141EECS14128Lecture #20Writing into a Static LatchWriting into a Static LatchCLKCLKCLKDQDCLKCLKDConverting into a MUXForcing the state(can implement as NMOS-only)Use the clock as a decoupling signal, that distinguishes between the transparent and opaque statesEE141EE141EECS14129Lecture #20PseudoPseudo--Static LatchStatic LatchDCLKCLKDEE141EECS14130Lecture #20EE141MuxMux--Based LatchesBased LatchesNegative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)CLK10DQ0CLK1DQInClkQClkQ ⋅+⋅=InClkQClkQ ⋅+⋅=EE141EE141EECS14131Lecture #20CLKCLKCLKDQMuxMux--Based LatchBased LatchEE141EECS14132Lecture #20MuxMux--Based LatchBased LatchCLKCLKCLKCLKQMQMNMOS only Non-overlapping clocksEE141EE141EECS14133Lecture #20NLatchLogicLogicPLatchφLatchLatch--Based DesignBased Design N latch is transparent when Φ = 0 P latch is transparent when Φ = 1EE141EECS14134Lecture #2010DCLKQMMaster01CLKQSlaveQMQDCLKTwo opposite latches trigger on edgeAlso called master-slave latch pair MasterMaster--Slave (EdgeSlave (Edge--Triggered) Triggered) RegisterRegisterEE141EE141EECS14135Lecture #20MasterMaster--Slave RegisterSlave RegisterQMQDCLKT2I2T1I1I3T4I5T3I4I6Multiplexer-based latch pairEE141EECS14136Lecture #20ClkClk--Q DelayQ DelayDQCLK20.50.51.52.5tclk-q(LH)0.5 1 1.5 22.50time, nsecVoltstclk-q(HL)EE141EE141EECS14137Lecture #20Setup TimeSetup TimeDQQMCLKI22 T22 0.5Volts0.00.2 0.4time (nsec)(a) Tsetup5 0.21 nsec0.6 0.8 100.51.01.52.02.53.0DQQMCLKI22 T22 0.5Volts0.00.2 0.4time (nsec)(b) Tsetup5 0.20 nsec0.6 0.8


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Berkeley ELENG 141 - Multipliers

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