1EE141 – Fall 2005Lecture 21Sequential CircuitsSequential CircuitsEE141 2Announcements Hardware lab this week Project 2 launch• Due Dec 6th– oral presentations Hw 8• Due Fr 5pm Office hours back to Th 1:30-3:30pm2Project 2Project 2EE141 4Project 2 Goal: Design an 8-bit Adder with Minimum Speed * Layout Area• Process: 0.25 µm CMOS• Unit sized inverter: Wp/Wn = 1u/0.5u• Choice of any logic style• Supply voltage: up to 2.5 V• All inputs ≤ Cinv• Output loads = 16 Cinv (unit-sized inverters)• Layout aspect ratio < 1.53EE141 5Design Phases Determine block diagram of adder that will best compromise propagation delay and area Design schematics of basic cells• Be structured Demonstrate functionality of adder Determine worst-case critical path Size transistors, and simulate critical path (make sure you include all loading factors needed) Layout, extract and re-simulate to evaluate impact of interconnectsEE141 6Reporting Presentations on Tu Dec 6; schedule TBD Prepare 5 slide presentation (PowerPoint template will be provided)• Choice of adder topology • Critical path analysis• Choice of logic style & transistor sizing• Layout techniques & LVS report• Summary of results 5-6’ per group oral presentation4EE141 7Grading Delay * Area product (80%) Power consumption (10%) Presentation (10%)EE141 8Class Material Last lecture• Power Today’s lecture• Sequential Circuits5Sequential LogicSequential LogicEE141 102 storage mechanisms• positive feedback• charge-basedCOMBINATIONALLOGICRegistersOutputsNext stateCLKQDCurrent StateInputsSequential Logic6EE141 11Latch versus RegisterDClkQDClkQ Register: edge-triggeredstores data when clock rises Clk ClkDDQQ Latch: level-sensitiveclock is low - hold modeclock is high - transparentEE141 12Naming Convention In our book, latch is level sensitive, register is edge-triggered There are many different naming conventions Many books call edge-triggered elements flip-flops7EE141 13LatchesInclkInOutPositive LatchCLKDGQOutOutstableOutfollows InInclkInOutNegative LatchCLKDGQOutOutstableOutfollows InEE141 14NLatchLogicLogicPLatchφLatch-Based Design N latch is transparent when Φ = 0 P latch is transparent when Φ = 18EE141 15Timing DefinitionstCLKtDtc→qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQEE141 16Characterizing TimingRegisterLatchClkDQtC→QClkDQtC→QtD→Q9EE141 17FF’sLOGICtp,combφAlso:tcdreg+ tcdlogic> tholdtcd: contamination delay = minimum delaytclk-Q+ tp,comb+ tsetup= TMaximum Clock FrequencyEE141 18Vi1Vo2Vo2 =Vi1Vo1=Vi2Vo1Vi1ACBVi25Vo1Vo2Vi25Vo1Vi1=Vo2Positive Feedback: Bi-Stability10EE141 19Gain should be larger than 1 in the transition regionACdBVi25Vo1Vi15Vo2ACdBVi25Vo1Vi15Vo2Meta-StabilityEE141 20Writing into a Static LatchCLKCLKCLKDQDCLKCLKDConverting into a MUXForcing the state(can implement as NMOS-only)Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states11EE141 21Cross-Coupled PairsForbidden StateSSRQQQQRSQQ00Q101001010110RQNOR-based set-resetThe “Overpowering” ApproachEE141 22Cross-Coupled NANDSQRQM1M2M3M4QM5SM6CLKM7RM8CLKVDDQCross-coupled NANDsAdded clockThis is not used in datapaths any more,but is a basic building memory cell12EE141 23Sizing IssuesOutput voltage dependenceon transistor widthTransient response4.03.53.0W/L5 and 6(a)2.52.00.00.51.01.52.0Q (Volts)time (ns)(b)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2012W = 1 mµ3VoltsQ SW = 0.9 mµW = 0.8 mµW = 0.7 mµW = 0.6 mµW = 0.5 mµEE141 24Pseudo-Static LatchDCLKCLKD13EE141 25Mux-Based LatchesNegative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)CLK10DQ0CLK1DQInClkQClkQ ⋅+⋅=InClkQClkQ ⋅+⋅=EE141 26CLKCLKCLKDQMux-Based Latch14EE141 27Mux-Based LatchCLKCLKCLKCLKQMQMNMOS only Non-overlapping clocksEE141 28Storage MechanismsDCLKCLKQDynamicCLKCLKCLKDQStatic15EE141 2910DCLKQMMaster01CLKQSlaveQMQDCLKTwo opposite latches trigger on edgeAlso called master-slave latch pair Master-Slave (Edge-Triggered) RegisterEE141 30Master-Slave RegisterQMQDCLKT2I2T1I1I3T4I5T3I4I6Multiplexer-based latch pair16EE141 31Clk-Q DelayDQCLK2 0.50.51.52.5tc 2 q(lh)0.5 1 1.5 22.50time, nsecVoltstc 2 q(hl)EE141 32Setup TimeDQQMCLKI22 T22 0.5Volts0.00.2 0.4time (nsec)(a) Tsetup5 0.21 nsec0.6 0.8 100.51.01.52.02.53.0DQQMCLKI22 T22 0.5Volts0.00.2 0.4time (nsec)(b) Tsetup5 0.20 nsec0.6 0.8 100.51.01.52.02.53.017EE141 33Data-to-Output Delay Sum of setup time and Clk-Q delay is the only true measure of performance w.r.t. system speed T = TClk-Q+ TLogic+ Tsetup+ TskewD QClkD QClkLogicNTLogicTClk-QTSetupTTD-Q=TClk-Q + TSetupEE141 34More Precise Setup TimetD 2 CttttC 2 Q1.05tC 2 QtSutHClkDQ(b)(a)18EE141 35Clk-Q DelayTSetup-1TClk-QTimeSetup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)DCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1EE141 36Clk-Q DelayTSetup-1TClk-QTimeTimet=0ClockDataTSetup-1Setup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)DCNQMCPD1SMInv1Inv2TG119EE141 37Clk-Q DelayTSetup-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1Setup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)EE141 38Clk-Q DelayTSetup-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1Setup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)20EE141 39Timet=0ClockDataTSetup-1DCNQMCPD1SMInv1Inv2TG1Setup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)Clk-Q DelayTSetup-1TClk-QTimeEE141 40Setup-Hold Time IllustrationsHold-1 caseDCNQMCPD1SMInv1Inv2TG1Timet=0DataClockTHold-10Clk-Q DelayTHold-1TClk-QTime21EE141 41Clk-Q DelayTHold-1TClk-QTimeTimet=0DataClockTHold-1Setup-Hold Time IllustrationsHold-1 caseDCNQMCPD1SMInv1Inv2TG10EE141 42Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0DataClockTHold-1Setup-Hold Time IllustrationsHold-1 case022EE141 43Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockTHold-1DataSetup-Hold Time IllustrationsHold-1 case0EE141 44Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockTHold-1DataSetup-Hold Time IllustrationsHold-1 case0⇒23EE141 45050100150200250300350-200 -150 -100 -50 0 50 100 150 200Data-Clk [ps]Clk-Output [ps]Setup HoldClk-Q Delay versus Setup and Hold TimesSampling WindowEE141 46DQT1I1CLKCLKT2CLKCLKI2I3I4Reduced Clock Load Master-Slave Register24EE141 47Avoiding Clock OverlapCLKCLKAB(a) Schematic diagram(b) Overlapping clock pairsXDQCLKCLKCLKCLKEE141
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