EE1411EECS1411Lecture #3EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 3Lecture 3Switches, Inverters,Switches, Inverters,and Design Metricsand Design MetricsEE1412EECS1412Lecture #3Administrative StuffAdministrative Stuff Discussions start this week (Fri.) Labs start next week Everyone should have an EECS instructional account Homework #1 is due today Homework #2 due next ThursdayEE1413EECS1413Lecture #3Class MaterialClass Material Last lecture Basics of IC manufacturing, cost Today’s lecture Transistor as switches Building an inverter Design metricsEE1414EECS1414Lecture #3What is a Transistor?What is a Transistor?|VGS|An MOS Transistor|VGS| ≥ |VT|SDRonA Switch!SDGEE1415EECS1415Lecture #3Switch Model of MOS TransistorSwitch Model of MOS Transistor|VGS|SDG|VGS| < |VT||VGS| > |VT|RonSDSDGGEE1416EECS1416Lecture #3NMOS and PMOSNMOS and PMOSVGS> 0SDGVGS< 0SDGNMOS Transistor PMOS TransistorEE1417EECS1417Lecture #3Building a CMOS inverterBuilding a CMOS inverterEE1418EECS1418Lecture #3Design MetricsDesign Metrics How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Speed/Performance (delay, frequency) PowerEE1419EECS1419Lecture #3ReliabilityReliability The real world is analog All physical quantities you deal with as a circuit designer are actually continuous Thus, even a “digital” signal can be noisy:i(t)Inductive coupling Capacitive coupling Power and groundnoisev(t)VDDEE14110EECS14110Lecture #3Noise and Digital SystemsNoise and Digital Systems Circuit needs to works despite “analog” noise Digital gates can reject noise This is actually how digital systems are defined Digital system is one where: Discrete values mapped to analog levels and back All the elements (gates) can reject noise– For “small” amounts of noise, output noise is less than input noise Thus, for sufficiently “small” noise, the system acts as if it was noiselessEE14111EECS14111Lecture #3Noise RejectionNoise RejectionGain = ∞VinVoutVDD/2VDDVDDGain = 0Gain = 0 To see if a gate rejects noise Look at its DC voltage transfer characteristic (VTC) See what happens when input is not exactly 1 or 0 Ideal digital gate: Noise needs to belarger than VDD/2 to have any effecton gate outputEE14112EECS14112Lecture #3More Realistic VTCMore Realistic VTCV(in)V(out)VOHVOLVMVOHVOLfV(out)=V(in)Switching ThresholdNominal Voltage LevelsVOH = f(VOL)VOL = f(VOH)VM = f(VM)EE14113EECS14113Lecture #3Voltage MappingVoltage MappingVILVIHVinSlope = -1Slope = -1VOLVOHVout“0”VOLVILVIHVOHUndefinedRegion“1”EE14114EECS14114Lecture #3Definition of Noise MarginsDefinition of Noise MarginsUndefinedRegionNoise margin high:NMH= VOH–VIHNoise margin low:NML= VIL–VOLGate OutputGate InputNMLNMH“0”“1”VOLVOHVILVIH(Stage M) (Stage M+1)EE14115EECS14115Lecture #3Digital Gate Noise Reduction: Digital Gate Noise Reduction: Regenerative PropertyRegenerative PropertyA chain of invertersv0v1v2v3v4v5v62V (Volt)4v0v1v2t (nsec)0211356 8 10Simulated responseEE14116EECS14116Lecture #3Regenerative Property (Another View)Regenerative Property (Another View)v0v1v3finv(v)f(v)v3outv2inRegenerativeNon-Regenerativev2v1f(v)finv(v)v3outv0inEE14117EECS14117Lecture #3FanFan--in and Fanin and Fan--outoutNFan-out NFan-in MMThere is a modified definition of fan-out for CMOS logicEE14118EECS14118Lecture #3Key Reliability PropertiesKey Reliability Properties Absolute noise margin values are not the only things that matter e.g., floating (high impedance) nodes are more easily disturbed than low impedance nodes (in terms of voltage) Noise immunity (i.e., how well the gate suppresses noise sources) needs to be considered too Summary of some key reliability metrics: Noise transfer functions & margin (ideal: gain = ∞, margin = Vdd/2) Output impedance (ideal: Ro= 0) Input impedance (ideal: Ri= ∞)EE14119EECS14119Lecture #3Example: An OldExample: An Old--time Invertertime InverterNMHVin(V)Vout(V)NMLVM0.01.02.03.04.05.01.0 2.0 3.0 4.0 5.0EE14120EECS14120Lecture #3Example: An OldExample: An Old--time Invertertime Inverter VOH= 3.6V VOL= 0.4V VIL= 0.6V VIH= 2.3V NMH= VOH– VIH= 1.3V NML= VIL– VOL= 0.2VEE14121EECS14121Lecture #3Performance: Delay DefinitionsPerformance: Delay DefinitionsVouttftpHLtpLHtrtVint90%10%50%50%EE14122EECS14122Lecture #3FanoutFanoutof Four (FO4) Delayof Four (FO4) DelaytFO4 Want a way to characterize the delay of a circuit (roughly) independent of technology Most common metric: Delay of an inverter driving four copies of itself (tFO4)EE14123EECS14123Lecture #3A FirstA First--Order RC NetworkOrder RC NetworkvoutvinCRtp= ln (2) τ = 0.69 RCImportant model – matches delay of an inverterEE14124EECS14124Lecture #3Power DissipationPower DissipationInstantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)Peak power: Ppeak= VsupplyipeakAverage power: ()∫∫++==TttTttsupplysupplyavedttiTVdttpTP )(1EE14125EECS14125Lecture #3““PowerPower--DelayDelay””and Energyand Energy--DelayDelay Want low power and low delay, so how about optimizing the product of the two? So-called “Power-Delay Product” Power·Delay is by definition Energy Optimizing this pushes you to go as slow as possible Alternative gate metric: Energy-Delay Product EDP = (Pav·tp)·tp= E·tpEE14126EECS14126Lecture #3Energy in CMOSEnergy in CMOSvoutvinCLR The voltage on CLeventually settles to VDD Thus, charge stored on the capacitor is CLVDD This charge has to flow out of the power supply So, energy is just Q·VDD=(CLVDD)·VDDEE14127EECS14127Lecture #3Energy (the harder way)Energy (the harder way)voutvinCLR() ()∫∫∫====→DDVDDLoutLDDTTDDDDDDVCdvCVdttiVdttPE020010() ()∫∫∫====DDVDDLoutoutLTTLoutCCVCdvvCdttivdttPE020021EE14128EECS14128Lecture #3SummarySummary Understanding the design metrics that govern digital design is crucial Cost Robustness Performance/speed Power and energy dissipationEE14129EECS14129Lecture #3Next LectureNext Lecture Detailed CMOS switch model Building gates with switches Design
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