University of California BerkeleyEE 141 Spring 2008 Laboratory Exercise 3 Post-Layout SimulationPage 1 Page 3 II. Circuit Extraction Run the design rule checker (DRC) on the layout to verify that all the design rules are met. (See the previous laboratory exercise on how to run DRC). The next step is to extract the transistor information from the layout itself. To perform the circuit extraction, click on Verify → Extract… from the menu bar to bring up the Extractor window. Make sure the rules file is set to: /home/ff/ee141/gpdk090_v3.9/diva/divaEXT.rul and the Rules Library check box is unchecked. Click OK to run the extractor. This will extract the transistor and interconnect information from the layout and create the extracted cell view of your inverter. After extraction, your CIW window should display: You can view the results of the extraction by opening the extracted cell view using the library manager. Make sure that the Rules Library box is unchecked and the correct rules file is specified. Open the extracted view to see the results of the circuit extraction.Close the extracted view. We will now perform LVS. III. Layout and Schematic Comparison (LVS) In order to verify that the layout matches the schematic, we use the layout-vs.-schematic (LVS) tool. This tool formally checks if the layout and schematic are topologically equivalent. To run LVS, select Verify → LVS… from the menu bar to open the Artist LVS window. Fill in the fields as shown below. Make sure the rules file is set to: /home/ff/ee141/gpdk090_v3.9/diva/divaLVS.rul and the Rules Library check box is unchecked. The extracted view shows the nodes and transistors recognized by the extraction tool. This can then be simulated using Spectre. Fill in the fields of the Artist LVS window as shown.Click on the Run button at the bottom of the Artist LVS window to start the LVS process. When the process completes, the Analysis Job Succeeded window pops up. Click OK to dismiss this window. To view the results of the comparison, click on the Output button at the bottom of the Artist LVS window. The LVS results window appears. Make sure that the ‘The net-lists match.’ line appears in the report window. This means that the schematic and the layout are topologically equivalent. Any mismatch between the layout and schematic will be indicated in this report. Close this window as well as the Artist LVS window to proceed to the next step of this laboratory exercise.Page 1 Page 3 UC Berkeley EE 141 Fall 2008 Last modified: 9/13/2008 1:24 PM by Abhinav
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