1EE141Dynamic operation ofMOS transistorPropagation DelayEE141- Spring 2003Lecture 6EE141Important!Homework 2 is due today.Homework 3 will be posted today.2EE141Today’s lectureThe MOS transistor characteristics fortransient analysisPropagation delayPower dissipationEE141Summary of last lecture0 0.5 1 1.5 2 2.500.511.522.5Vin (V)Vout(V)3EE141Impact of Process Variations0 0.5 1 1.5 2 2.500.511.522.5Vin(V)Vout(V)Good PMOSBad NMOSGoodNMOSBad PMOSNominalEE141MOS CapacitancesDynamic Behavior4EE141Dynamic Behavior of MOS TransistorDSGBCGDCGSCSBCDBCGBEE141The Gate Capacitancetoxn+n+Cross sectionLGate oxidexdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+W5EE141Gate CapacitanceSDGCGCSDGCGCSDGCGCCut-offResistive SaturationMost important regions in digital design: saturation and cut-offEE141Gate CapacitanceWLCoxWLCox22WLCox3CGCCGCSVDS/(VGS-VT)CGCD01CGCCGCS=CGCDCGC BWLCoxWLCox2VGSCapacitance as a function of VGS(withVDS= 0)Capacitance as a function of thedegree of saturation6EE141Measuring the Gate Cap⫺1.5 ⫺1 ⫺0.5 0345678910⫻ 10⫺162VGS (V)VGSGate Capacitance (F)0.5 1 1.5 2⫺2IEE141Diffusion CapacitanceBottomSide wallSide wallChannelSourceNDChannel-stop implantNA⫹Substrate NAWxjLS7EE141Junction CapacitanceEE141Linearizing the Junction CapacitanceReplace non-linear capacitance bylarge-signal equivalent linear capacitancewhich displaces equal chargeover voltage swing of interest8EE141Capacitances in 0.25µmCMOS processEE141.MODEL Parameters MOS1.MODEL Modname NMOS/PMOS <VTO=VTO...>9EE141Two InvertersPolysiliconInOutMetal1VDDGNDPMOSNMOS1.2µm=2λλλλEE141Two Inverters (modern view)VDD10EE141Computing the CapacitancesFanoutVoutVinCLSimplifiedModelM3M4M1M2CwCg3Cdb1Cg4Vout2Cdb2VDDVDDVinVoutCgd12EE141The Miller EffectVinM1Cgd1Vout∆V∆VVinM1Vout∆V∆V2Cgd1“A capacitor experiencing identical but opposite voltage swingsat both its terminals can be replaced by a capacitor to ground,whose value is two times the original value.”11EE141Computing the CapacitancesEE141Propagation Delay12EE141CMOS Inverter Propagation DelayApproach 1VDDVoutVin=VDDCLIavtpHL=CLVswing/2IavCLknVDD~EE141CMOS Inverter Propagation DelayApproach 2VDDVoutVin=VDDRonCLtpHL= f(Ron.CL)=0.69RonCLtVoutVDDRonCL10.5ln(0.5)0.3613EE1410 0.5 1 1.5 2 2.5x 10-10-0.500.511.522.53t (sec)Vout(V)Transient Responsetp=0.69CL(Reqn+Reqp)/2?tpLHtpHLEE141Design for PerformanceKeep capacitances smallIncrease transistor sizes» watch out for self-loading!Increase VDD(?)14EE141Delay as a function of VDD0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.411.522.533.544.555.5VDD(V)tp(normalized)EE1412 4 6 8 10 12 1422.22.42.62.833.23.43.63.8x 10-11Stp(sec)Device Sizing(for fixed load)Self-loading effect:Intrinsic capacitancesdominate15EE1411 1.5 2 2.5 3 3.5 4 4.5 533.544.55x 10-11βtp(sec)NMOS/PMOS ratiotpLHtpHLtpβ =Wp/WnEE141Impact of Rise Time on DelaytpHL(nsec)0.350.30.250.20.15trise(nsec)10.80.60.40.20tp= tstep(i)+ηtstep(i-1)16EE141The Sub-Micron MOS TransistorThreshold VariationsSubthreshold ConductionParasitic ResistancesEE141Threshold VariationsVTLLong-channel thresholdLow VDSthresholdThreshold as a function ofthe length (for lowVDS)Drain-induced barrier lowering(for low L)VDSVT17EE141Sub-Threshold Conduction0 0.5 1 1.5 2 2.510-1210-1010-810-610-410-2VGS(V)ID(A)VTLinearExponentialQuadraticTypical values for S:60 .. 100 mV/decadeThe Slope FactoroxDnkTqVDCCneIIGS+=1,~0S is ∆VGSfor ID2/ID1=10EE141Sub-Threshold IDvs VGSVDSfrom 0 to 0.5V−=−kTqVnkTqVDDSGSeeII 1018EE141Sub-Threshold IDvs VDS()DSkTqVnkTqVDVeeIIDSGS⋅+−=−λ110VGSfrom 0 to 0.3VEE141Next LectureOptimizing for PerformancePower dissipation in CMOS
View Full Document
Unlocking...