EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 15Lecture 15Logical effortLogical effortEE1412EECS141AnnouncementsAnnouncements Hardware lab this week Lab 4, 5 reports due next week Homework #6 due next Tuesday Project launch next weekEE1412EE1413EECS141Midterm 1Midterm 1 Hi: 48 (G) 37 (UG) Lo: 13 (UG) Average: 28 Median: 29EE1415EECS141Class MaterialClass Material Last lecture Design for speed Today’s lecture Logical effort Reading (Chapter 6)EE1413EE1416EECS141Fast Complex Gates:Fast Complex Gates:Design Technique 2Design Technique 2 Transistor orderingC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical path critical pathcharged10→1chargedcharged1delay determined by time to discharge CL, C1and C2delay determined by time to discharge CL110→1chargeddischargeddischargedEE1417EECS141Fast Complex Gates:Fast Complex Gates:Design Technique 3Design Technique 3 Alternate logic structuresF = ABCDEFGHEE1414EE1418EECS141Fast Complex Gates:Fast Complex Gates:Design Technique 4Design Technique 4 Isolating fan-in from fan-out using buffer insertionCLCLEE1419EECS141Fast Complex Gates:Fast Complex Gates:Design Technique 5Design Technique 5 Reducing the voltage swing linear reduction in delay also reduces power consumption But the following gate is much slower! Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design)tpHL= 0.69 (3/4 (CL VDD)/ IDSATn)= 0.69 (3/4 (CL Vswing)/ IDSATn)EE1415EE14110EECS141Logical Logical EffortEffortEE14111EECS141Buffer ExampleBuffer Example()∑=+=NiifDelay11For given N: Ci+1/Ci= Ci/Ci-1To find N: Ci+1/Ci~ 4How to generalize this to any logic path?CL = CN+1In Out12 N(in units of τinv)fi= Ci+1/CiC1C2CNEE1416EE14112EECS141Logical EffortLogical Effort()fgpCCCRkDelayinLunitunit⋅+=⎟⎟⎠⎞⎜⎜⎝⎛+⋅=τγ1p – intrinsic delay (3kRunitCunitγ) - gate parameter ≠ f(W)g – logical effort (kRunitCunit) – gate parameter ≠ f(W)f – electrical effort (effective fanout)Normalize everything to an inverter:ginv=1, pinv= γDivide everything by τinv(everything is measured in unit delays τinv)Assume γ = 1.EE14113EECS141Delay in a Logic GateDelay in a Logic GateGate delay:d = h + peffort delayintrinsic delayEffort delay:h = g flogical efforteffective fanout = Cout/CinLogical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate sizeEE1417EE14114EECS141Logical EffortLogical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexityEE14115EECS141Logical EffortLogical EffortLogical effort is the ratio of input capacitance of a gate (input) to the input capacitance of an inverter with the same output currentg = 1g = 4/3g = 5/3BAABFVDDVDDABABFVDDAAF1222221144Inverter 2-input NAND 2-input NOREE1418EE14116EECS141Logical Effort of GatesLogical Effort of GatesFan-out (f)Normalized delay (d)t1 2 3 4 5 6 7 pINVtpNANDF(Fan-in)g=p=d=g=p=d=EE14118EECS141Logical Effort of GatesLogical Effort of GatesIntrinsicDelayEffortDelay12345Fanout f12345Inverter:g = 1;p = 12-input NAND:g = 4/3;p = 2Normalized DelayEE1419EE14119EECS141Add Branching EffortAdd Branching EffortBranching effort: pathonpathoffpathonCCCb−−−+=Coff-pathCon-pathEE14120EECS141Multistage NetworksMultistage NetworksStage effort: hi= gifiPath electrical effort: F = Cout/CinPath logical effort: G = g1g2…gNBranching effort: B = b1b2…bNPath effort: H = GFBPath delay D = Σdi= Σpi+ Σhi()∑=⋅+=NiiiifgpDelay1EE14110EE14121EECS141Optimum Effort per StageOptimum Effort per StageHhN=When each stage bears the same effort:NHh =()PNHpfgDNiii+=+=∑/1ˆMinimum path delayEffective fanout of each stage:iighf=Stage efforts: g1f1= g2f2= … = gNfNEE14122EECS141Optimal Number of StagesOptimal Number of StagesFor a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing∑+=iNpNHD/1NHhˆ/1=The ‘best stage effort’Remember: we can always add inverters to the end of the chainis around 4 (3.6 with γ=1)EE14111EE14123EECS141Logical EffortLogical EffortFrom Sutherland, SproullEE14124EECS141Example: Optimize PathExample: Optimize PathEffective fanout, F =G = H =h =a =b = 1abc5g = 1f = ag = 5/3f = b/ag = 5/3f = c/bg = 1f = 5/cEE14112EE14126EECS141Example Example ––88--Input ANDInput ANDEE14127EECS141Method of Logical EffortMethod of Logical Effort Compute the path effort: H = GBF Find the best number of stages N ~ log4H Compute the stage effort h = H1/N Sketch the path with this number of stages Work either from either end, find sizes: Cin= Cout*g/hReference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.EE14113EE14128EECS141Next LectureNext Lecture Memory Project
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