EE1411EECS1411Lecture #25EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 25Lecture 25I/O IssuesI/O IssuesPower DistributionPower DistributionEE1412EECS1412Lecture #25AnnouncementsAnnouncements Project phase 3 Poster session tomorrow starting at 3:30pm Final report: Mon. Dec. 7th5:00pm Optional HW#9 posted HKN surveys end of this Thurs. lecture Attendance required Final exam: Tues. Dec. 15th, 5-8:00pm, Location TBD Review session most likely on Mon. Dec. 14thEE1413EECS1413Lecture #25Class MaterialClass Material Last lecture Clock distribution Today’s lecture I/O Design Power DistributionEE1414EECS1414Lecture #25I/O DesignI/O DesignEE1415EECS1415Lecture #25Chip PackagingChip PackagingChipLL ´Bonding wireMountingcavityLeadframePin•Bond wires (~25µm) are used to connect the package to the chip• Pads are arranged in a frame around the chip• Pads are relatively large (~100µm in 0.25µm technology),with large pitch (100µm)•Many chips are ‘pad limited’EE1416EECS1416Lecture #25Pad FramePad FrameLayout Die PhotoEE1417EECS1417Lecture #25Bonding Pad DesignBonding Pad DesignBonding PadOutInVDDGND100 µmGNDOutEE1418EECS1418Lecture #25Chip PackagingChip Packaging An alternative is ‘flip-chip’: Pads are distributed around the chip The soldering balls are placed on pads The chip is ‘flipped’ onto the package Pads still large– But can have many more of themEE1419EECS1419Lecture #25ESD ProtectionESD Protection When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate –need guard rings to pick it up.EE14110EECS14110Lecture #25Pads + ESD ProtectionPads + ESD ProtectionDiodePADVDDRD1D2XCEE14111EECS14111Lecture #25Power Power DistributionDistributionEE14112EECS14112Lecture #25Power Supply ImpedancePower Supply Impedance No voltage source is ideal - ||Z|| > 0 Two principal elements increase Z: Resistance of supply lines (IR drop) Inductance of supply lines (L⋅di/dt drop)EE14113EECS14113Lecture #25Technology (µm)0.10.20.30.40.50.610-310-210-1100Scaling and Supply ImpedanceScaling and Supply Impedance Typical target for supply impedance is to get 5-10% variation of nominal supply (e.g., 100mV for 1V supply) In traditional scaling Vdddrops while power stays constant This forced drastic drop in supply impedance Vdd↓, Idd↑ Æ |Zrequired| ↓↓ Today’s chips: |Zrequired| ≈ 1 mΩ!Impedance Requirements of High-Performance ProcessorsRequired Impedance (Ω)EE14114EECS14114Lecture #25IR Drop ExampleIR Drop Example Intel Pentium 4: ~103W at ~1.275V Idd= 81Amps For 10% IR drop, total distribution resistance must be less than 1.6mΩ On-chip wire R ≈ 20mΩ/sq. (thick metal) Can’t meet R requirement even with multiple, complete layers dedicated to power Main motivation for flip-chip packagingEE14115EECS14115Lecture #25Power DeliveryPower Delivery Achieving such low impedance requires a lot of resources: ~70% of package pins just for power Top 2-3 (thick) metal layersEE14116EECS14116Lecture #25Not Just Impedance Not Just Impedance --ElectromigrationElectromigration On-chip wires: current limited to ~1mA/µm for 5-7 year lifetimeEE14117EECS14117Lecture #25OnOn--Chip Power DistributionChip Power Distribution Power network usually follows pre-defined template (often referred to as “power grid”)VDDGnd VDDGndVDDGndVDDGndEE14118EECS14118Lecture #253 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)3rd “coarse and thick” metal layer added to thetechnology for EV4 designPower supplied from two sides of the die via 3rd metal layer2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routingMetal 3Metal 2Metal 1Courtesy CompaqEE14119EECS14119Lecture #254 Metal Layers Approach (EV5)4 Metal Layers Approach (EV5)4th “coarse and thick” metal layer added to thetechnology for EV5 designPower supplied from four sides of the dieGrid strapping done all in coarse metal90% of 3rd and 4th metals used for power/clock routingMetal 3Metal 2Metal 1Metal 4Courtesy CompaqEE14120EECS14120Lecture #252 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/VssLowers on-chip inductance6 Metal Layer Approach 6 Metal Layer Approach ––EV6EV6Metal 4Metal 2Metal 1RP2/VddRP1/VssMetal 3Courtesy CompaqEE14121EECS14121Lecture #25SUPPLYBoardwiringBondingwireDecouplingcapacitorCHIPCd12Decoupling CapacitorsDecoupling Capacitors On the board (right under the supply pins) On the chip (under the supply straps, near large buffers)Decoupling capacitors are added:EE14122EECS14122Lecture #25Decoupling CapacitorsDecoupling Capacitors Under the
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