TERM PROJECT: 32x64 SRAM DesignEECS 141: Digital Integrated Circuits - Fall 2008Report Cover SheetTERM PROJECT: 32x64 SRAM DesignReport 3 – Putting it all Together and OptimizationDue Monday, December 8, 2008 by 5:00pm in the drop box.NamesDescription of Optimization Objectives(You should describe what your optimization goals were here: e.g., minimum power, maximum speed, good balance of speed/area, etc.)Parameter Value UnitsCell Area µm2Calculated Adder/Subtractor Delay psSimulated Adder/Subtractor Delay psCalculated Decoder Delay psSimulated Decoder Delay psSimulated WL-Out Delay psTotal Simulated Delay psCalculated Power Dissipation µWSimulated Power Dissipation µWTotal Area µm2GRADEApproach, result and correctness (65%)Report (35%)TOTALComplete SRAM Design(Annotated schematic or block diagram and layout of the complete array.Simulation showing functional read with worst-case delay and timing of criticalsignals, including any clocks you used. You should provide highlights of the keyoptimizations/design decisions you made here - e.g., using domino logic in theadder/subtractor, reducing the supply voltage for the SRAM, etc.)SRAM Cell Design(Schematic and layout of the SRAM cell. Read and write margins/butterfly plots.You can skip this section if you did not modify the SRAM cell we gave you, butotherwise you should explain any changes you made from the design given to you inphase 1. )Decoder Design(Annotated schematics with gate sizes and layout of the decoder. Simulation showingworst-case propagation delay, hand calculation of decoder delay and power.Explain your design decisions and approach. You do not need to provide transistorlevel schematics of any standard gates you used, but you should provide schematicsof any new/non-obvious gates.)Adder/Subtractor Design(Annotated schematics with gate sizes and layout of the adder/subtractor. Identifythe critial path and show hand calculation of delay and power. Worst-case delaysimulation showing the critical signals. Explain your design decisions and approach.Schematics of any new and non-obvious gates.)Appendix(This space has been provided for you to include relevant information that did notfit into the previous sections. This is a good place to put any additional analyses youdid that didn’t fit or you weren’t sure where to put. For example, you might providea more detailed power break-down/estimate of each of the major blocks, logicaleffort sizing calculations of the complete adder/subtractor/decoder path, outputbuffer/multiplexor sizing,
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