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Berkeley ELENG 141 - Lecture 20 Adders

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EE1411EECS1411Lecture #20EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 20Lecture 20AddersAddersEE1412EECS1412Lecture #20AnnouncementsAnnouncements Midterm 2: Thurs. Nov. 5th, 6:30-8:00pm, 2060 Valley LSB Exam starts at 6:30pm sharp Review session: Wed., Nov. 4th, 6:00-7:00pm, 247 Cory Project phase 2 out this Thurs., due next Thurs.EE1413EECS1413Lecture #20Class MaterialClass Material Last lecture Dynamic logic Today’s lecture Adders Reading Chapter 11EE1414EECS1414Lecture #20AddersAddersEE1415EECS1415Lecture #20An Intel MicroprocessorAn Intel Microprocessor9-1 Mux9-1 Mux5-1 Mux2-1 Muxck1CARRYGENSUMGEN+ LU1000umbs0s1g64sumsumbLU : LogicalUnitSUMSELato Cachenode1REGItanium has 6 64-bit integer execution units like thisEE1416EECS1416Lecture #20BitBit--Sliced DesignSliced DesignBit 3Bit 2Bit 1Bit 0RegisterAdderShifterMultiplexerControlData-InData-OutTile identical processing elementsEE1417EECS1417Lecture #20Itanium Integer Itanium Integer DatapathDatapathFetzer, Orton, ISSCC’02EE1418EECS1418Lecture #20Data Paths Are Thermal HogsData Paths Are Thermal HogsEE1419EECS1419Lecture #20FullFull--AdderAdderABCoutSumCinFulladderkillkillEE14110EECS14110Lecture #20The Binary AdderThe Binary AdderSABCi⊕⊕=A=BCiABCiABCiABCi+++CoAB BCiACi++=EE14111EECS14111Lecture #20Express Sum and Carry as a function of P, G, KExpress Sum and Carry as a function of P, G, KDefine 3 new variables which ONLY depend on A, BGenerate (G) = ABPropagate (P) = A ⊕BKill = ABCan also derive expressions for Sand Cobased on K and PPropagate (P) = A +BNote that we will sometimes use an alternate definition for EE14112EECS14112Lecture #20Simplest Adder: RippleSimplest Adder: Ripple--CarryCarryWorst case delay linear with the number of bitsGoal: Make the fastest possible carry path circuitFA FA FA FAA0B0S0A1B1S1A2B2S2A3B3S3Ci,0Co,0(= Ci,1)Co,1Co,2Co,3td= O(N)tadder= (N-1)tcarry+ tsumEE14113EECS14113Lecture #20Complementary Static CMOS Full Adder: Complementary Static CMOS Full Adder: ““DirectDirect””ImplementationImplementation28 TransistorsABBACiCiAXVDDVDDA BCiBABVDDABCiCiABA CiBCoVDDSEE14114EECS14114Lecture #20Complementary Static CMOS Full AdderComplementary Static CMOS Full Adder28 TransistorsEE14115EECS14115Lecture #20Inversion PropertyInversion PropertyABSCoCiFAABSCoCiFAEE14116EECS14116Lecture #20Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting StagesExploit Inversion PropertyA3FA FA FAEven cell Odd cellFAA0B0S0A1B1S1A2B2S2B3S3Ci,0Co,0Co,1Co,3Co,2EE14117EECS14117Lecture #20A Better Structure: The Mirror AdderA Better Structure: The Mirror AdderVDDCiABBABAABKillGenerate"1"-Propagate"0"-PropagateVDDCiABCiCiBACiABBAVDDSCo24 transistorsEE14118EECS14118Lecture #20Sizing the Mirror Adder: Sizing the Mirror Adder: FanoutFanout• Since LE of carry gate is 2, want f of 2to get EF of 4• Use min. size sum gates to reduceload on carry.• Total load on carry gate is:Cload= CCi+ (6+6+9)Cload= 2CCiEE14119EECS14119Lecture #20Sizing the Mirror AdderSizing the Mirror Adder•Cload= CCi+ (6+6+9) = 2CCiÆ CCi= 21• Minimum size G and K stacks to reduce diffusion loadingEE14120EECS14120Lecture #20Mirror Adder SummaryMirror Adder Summary•The NMOS and PMOS chains are completely symmetrical. Maximum of two series transistors in the carry-generation gate.•When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. Reduction of the diffusion capacitances is particularly important.•Carry signals are critical - transistors connected to Ciare placed closest to the output.•Only the transistors in the (propagate) carry chain have to be optimized for speed. All transistors in the sum stage can be minimal size.EE14121EECS14121Lecture #20Transmission Gate Full AdderTransmission Gate Full AdderABPCiVDDAAAVDDCiAPABVDDVDDCiCiCoSCiPPPPPSum GenerationCarry GenerationSetupEE14122EECS14122Lecture #20Manchester Carry ChainManchester Carry ChainCoCiGiKiPiPiVDDEE14123EECS14123Lecture #20Dynamic Manchester Carry ChainDynamic Manchester Carry ChainCoCiGiKiPiPiVDDCoCiGiPiVDDφφEE14124EECS14124Lecture #20Manchester Carry ChainManchester Carry ChainEE14125EECS14125Lecture #20CarryCarry--Bypass AdderBypass AdderFA FA FA FAP0G1P0G1P2G2P3G3Co,3Co,2Co,1Co,0Ci,0FA FA FA FAP0G1P0G1P2G2P3G3Co,2Co,1Co,0Ci,0Co,3MultiplexerBP=PoP1P2P3Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.Also called Carry-SkipEE14126EECS14126Lecture #20CarryCarry--Bypass Adder (cont.)Bypass Adder (cont.)CarrypropagationSetupBit 0–3SumM bitstsetuptsumCarrypropagationSetupBit 4–7SumtbypassCarrypropagationSetupBit 8–11SumCarrypropagationSetupBit 12–15Sumtadder= tsetup+ (M-1)tcarry+ (N/M-1)tbypass+ (M-1)tcarry+ tsumEE14127EECS14127Lecture #20Carry Ripple versus Carry BypassCarry Ripple versus Carry BypassNtpripple adderbypass adder4..8EE14128EECS14128Lecture #20CarryCarry--Select AdderSelect AdderSetup"0" Carry Propagation"1" Carry PropagationMultiplexerSum GenerationCo,k-1Co,k+3"0""1"P,GCarry VectorEE14129EECS14129Lecture #20Carry Select Adder: Critical Path Carry Select Adder: Critical Path 01Sum GenerationMultiplexer1-Carry0-CarrySetupCi,0Co,3Co,7Co,11Co,15S0–3Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–1501Sum GenerationMultiplexer1-Carry0-CarrySetupS4–701Sum GenerationMultiplexer1-Carry0-Carry 0-CarrySetupS8–1101Sum GenerationMultiplexer1-CarrySetupS12–15EE14130EECS14130Lecture #20Linear Carry Select Linear Carry Select Setup"0" Carry "1" Carry MultiplexerSum Generation"0""1"Setup"0" Carry "1" Carry MultiplexerSum Generation"0""1"Setup"0" Carry "1" Carry MultiplexerSum Generation"0""1"Setup"0" Carry "1" Carry MultiplexerSum Generation"0""1"Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15S0-3S4-7S8-11S12-15Ci,0(1)(1)(5)(6) (7) (8)(9)(10)(5) (5) (5)(5)EE14131EECS14131Lecture #20Square Root Carry Select Square Root Carry Select Setup"0" Carry "1" Carry MultiplexerSum Generation"0""1"Setup"0" Carry "1" Carry MultiplexerSum Generation"0""1"Setup"0" Carry "1" Carry MultiplexerSum Generation"0""1"Setup"0" Carry "1" Carry MultiplexerSum Generation"0""1"Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13S0-1S2-4S5-8S9-13Ci,0(4) (5) (6) (7)(1)(1)(3) (4) (5) (6)MuxSumS14-19(7)(8)Bit 14-19(9)(3)MEE14132EECS14132Lecture #20Adder Delays Adder Delays --Comparison Comparison Square root selectLinear selectRipple adder20 40Ntp(in unit delays)60010020304050EE14133EECS14133Lecture #20Logarithmic (Tree)


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Berkeley ELENG 141 - Lecture 20 Adders

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