EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 3Lecture 3CMOS InverterCMOS InverterEE1412EECS141Administrative StuffAdministrative Stuff Discussions start this week Labs start next week Everyone should have an EECS instructional account http://www-inst.eecs.berkeley.edu/~inst/newusers.html Homework #1 is due today Homework #2 due next TuesdayEE1412EE1413EECS141Class MaterialClass Material Last lecture Basic metrics for IC design Today’s lecture Finish metrics (Chapter 1) Brief introduction to CMOS inverter operation (intro to Chapter 3) CMOS manufacturing process (Chapter 2) Reading (2.1-2.2, 3.3.1-3.3.2)EE1414EECS141FanFan--in and Fanin and Fan--outoutNFan-out NFan-in MMThere is a modified definition of fan-out for CMOS logicEE1413EE1415EECS141The Ideal GateThe Ideal GateRi = ∞Ro = 0Fanout = ∞NMH= NML= VDD/2g = ∞VinVoutEE1416EECS141Example: An OldExample: An Old--time Invertertime InverterNMHVin(V)Vout(V)NMLVM0.01.02.03.04.05.01.0 2.0 3.0 4.0 5.0EE1414EE1417EECS141Example: An OldExample: An Old--time Invertertime Inverter VOH= 3.6V VOL= 0.4V VIL= 0.6V VIH= 2.3V NMH= VOH– VIH= 1.3V NML= VIL– VOL= 0.2VEE1418EECS141EE1415EE1419EECS141Delay DefinitionsDelay DefinitionsVouttftpHLtpLHtrtVint90%10%50%50%EE14110EECS141Ring OscillatorRing Oscillatorv0v1v5v1v2v0v3v4v5T = 2 ×tp×NEE1416EE14111EECS141A FirstA First--Order RC NetworkOrder RC NetworkvoutvinCRtp= ln (2) τ = 0.69 RCImportant model – matches delay of an inverterEE14112EECS141EE1417EE14113EECS141Power DissipationPower DissipationInstantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)Peak power: Ppeak= VsupplyipeakAverage power: ()∫∫++==TttTttsupplysupplyavedttiTVdttpTP )(1EE14114EECS141Energy and EnergyEnergy and Energy--DelayDelayPower-Delay Product (PDP) =E = Energy per operation = Pav×tpEnergy-Delay Product (EDP) =quality metric of gate = E ×tpEE1418EE14115EECS141A FirstA First--Order RC NetworkOrder RC NetworkvoutvinCLR() ()∫∫∫====→DDVDDLoutLDDTTDDDDDDVCdvCVdttiVdttPE020010() ()∫∫∫====DDVDDLoutoutLTTLoutCCVCdvvCdttivdttPE020021EE14116EECS141SummarySummary Understanding the design metrics that govern digital design is crucial Cost Robustness Speed Power and energy dissipationEE1419EE14117EECS141CMOS InverterCMOS InverterEE14118EECS141The CMOS Inverter: A First GlanceThe CMOS Inverter: A First GlanceVinVoutCLVDDEE14110EE14119EECS141CMOS InverterCMOS InverterFirstFirst--Order DC AnalysisOrder DC AnalysisVOL= 0VOH= VDDVM= f(Rn, Rp)VDDVDDVin⫽VDDVin⫽0VoutVoutRnRpEE14120EECS141Simulated Inverter VTC (Spice)Simulated Inverter VTC (Spice)0 0.5 1 1.5 2 2.500.511.522.5Vin (V)Vout(V)EE14111EE14121EECS141CMOS Inverter: DC PropertiesCMOS Inverter: DC Properties VOH= VOL= VIL= VIH= NMH= NML= VM= EE14122EECS141CMOS Inverter: DC PropertiesCMOS Inverter: DC Properties VOH= VDD= 2.5V VOL= 0V VIL= 1.05V VIH= 1.45V NMH=1.05V NML= 1.05V VM= 1.2VEE14112EE14123EECS141CMOS Inverter: Transient ResponseCMOS Inverter: Transient ResponsetpHL= f(Ron.CL)= 0.69 RonCL(a) Low-to-high (b) High-to-lowVoutVoutRnRpVDDVDDVin =VDDVin =0CLCLEE14124EECS141CMOS PropertiesCMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during
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