1Digital Integrated CircuitsEE141Manufacturing ProcessCMOSManufacturingProcessDigital Integrated CircuitsEE141Manufacturing ProcessCMOS Process2Digital Integrated CircuitsEE141Manufacturing ProcessAModernCMOSProcessp-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2Dual-Well Trench-Isolated CMOS ProcessDigital Integrated CircuitsEE141Manufacturing ProcessCircuit Under DesignThis two-inverter circuit (of Figure 3.25 in the text) will bemanufactured in a twin-well process.VDDVDDVinVoutM1M2M3M4Vout23Digital Integrated CircuitsEE141Manufacturing ProcessCircuit LayoutDigital Integrated CircuitsEE141Manufacturing ProcessThe Manufacturing ProcessFor a great tour through the process and its different steps, checkhttp://www.fullman.com/semiconductors/semiconductors.htmlhttp://bwrc.eecs.berkeley.edu/Classes/IcBookFor a complete walk-through of the process (64 steps), check theBook web-page4Digital Integrated CircuitsEE141Manufacturing Processoxidationopticalmaskprocessstepphotoresist coatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotoresiststepper exposuredevelopmentTypical operations in a singlephotolithographic cycle (from [Fullman]).Photo-Lithographic ProcessDigital Integrated CircuitsEE141Manufacturing ProcessPatterning of SiO2Si-substrateSi-substrateSi-substrate(a) Silicon base material(b) After oxidation and depositionof negative photoresist(c) Stepper exposurePhotoresistSiO2UV-lightPatternedoptical maskExposed resistSiO2Si-substrateSi-substrateSi-substrateSiO2SiO2(d) After development and etching of resist,chemical or plasma etch of SiO2(e) After etching(f) Final result after removal of resistHardened resistHardened resistChemical or plasmaetch5Digital Integrated CircuitsEE141Manufacturing ProcessCMOS Process at a GlanceDefine active areasEtch and fill trenchesImplant well regionsDeposit and patternpolysilicon layerImplant source and drainregions and substrate contactsCreate contact and via windowsDeposit and pattern metal layersDigital Integrated CircuitsEE141Manufacturing ProcessCMOS Process Walk-Throughp+p-epi(a) Base material: p+ substratewith p-epi layerp+(c) After plasma etch of insulatingtrenches using the inverse oftheactiveareamaskp+p-epiSiO23SiN4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)6Digital Integrated CircuitsEE141Manufacturing ProcessCMOS Process Walk-ThroughSiO2(d) After trench filling, CMPplanarization, and removal ofsacrificial nitride(e) After n-well andVTpadjust implantsn(f) After p-well andVTnadjust implantspDigital Integrated CircuitsEE141Manufacturing ProcessCMOS Process Walk-Through(g) After polysilicon depositionand etchpoly(silicon)(h) After n+ source/drain andp+source/drain implants. Thesep+n+steps also dope the polysilicon.(i) After deposition of SiO2insulator and contact hole etch.SiO27Digital Integrated CircuitsEE141Manufacturing ProcessCMOS Process Walk-Through(j) After deposition andpatterning of first Al layer.Al(k) After deposition of SiO2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.AlSiO2Digital Integrated CircuitsEE141Manufacturing ProcessAdvanced Metalization8Digital Integrated CircuitsEE141Manufacturing ProcessAdvanced MetalizationDigital Integrated CircuitsEE141Manufacturing ProcessJan M. RabaeyDesign Rules9Digital Integrated CircuitsEE141Manufacturing Process3D PerspectivePolysiliconAluminumDigital Integrated CircuitsEE141Manufacturing ProcessDesign Rules! Interface between designer and processengineer! Guidelines for constructing process masks! Unit dimension: Minimum line width» scalable design rules: lambda parameter» absolute dimensions (micron rules)10Digital Integrated CircuitsEE141Manufacturing ProcessCMOS Process LayersLayerPolysiliconMetal1Metal2Contact To PolyContact To DiffusionViaWell (p,n)Active Area (n+,p+)Color RepresentationYellowGreenRedBlueMagentaBlackBlackBlackSelect (p+,n+)GreenDigital Integrated CircuitsEE141Manufacturing ProcessLayers in 0.25 µmCMOSprocess11Digital Integrated CircuitsEE141Manufacturing ProcessIntra-Layer Design RulesMetal2431090WellActive33Polysilicon22Different PotentialSame PotentialMetal1332Contactor ViaSelect2or62HoleDigital Integrated CircuitsEE141Manufacturing ProcessTransistor Layout1253Transistor12Digital Integrated CircuitsEE141Manufacturing ProcessVia’s and Contacts121ViaMetal toPoly ContactMetal toActive Contact1254322Digital Integrated CircuitsEE141Manufacturing ProcessSelect Layer133222WellSubstrateSelect3513Digital Integrated CircuitsEE141Manufacturing ProcessCMOS Inverter LayoutAA’np-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-A’AA’Digital Integrated CircuitsEE141Manufacturing ProcessLayout Editor14Digital Integrated CircuitsEE141Manufacturing ProcessDesign Rule Checkerpoly_not_fet to all_diff minimum spacing = 0.14 um.Digital Integrated CircuitsEE141Manufacturing ProcessSticks Diagram13InOutVDDGNDStick diagram of inverter• Dimensionless layout entities• Only topology is important• Final layout generated by“compaction”
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