1EE141CMOS LogicEE141- Spring 2003Lecture 14EE141Static Complementary CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPMOS onlyNMOS onlyPUN and PDN are dual logic networks……2EE141Standard CellsCell boundaryNWellCell height 12 metal tracksMetal track is approx. 3λ +3λPitch =repetitive distance between objectsCell height is “12 pitch”2λRails ~10λInOutVDDGNDEE141Standard CellsAOutVDDGNDB2-input NAND gateBVDDA3EE141Multi-Fingered TransistorsOne fingerTwo fingers (folded)Less capacitance, Less resistanceEE141Stick DiagramsContains no dimensionsRepresents relative positions of transistorsInOutVDDGNDInverterAOutVDDGNDBNAND24EE141Stick DiagramsCABX=C•(A+B)BACijjVDDXXiGNDABCPUNPDNABCLogic GraphEE141Two Versions of C • (A + B)XCAB ABCXVDDGNDVDDGND5EE141Consistent Euler PathjVDDXXiGNDABCABCEE141OAI22 Logic GraphCABX = (A+B)•(C+D)BADVDDXXGNDABCPUNPDNCDDABCD6EE141Example: x = ab+cdGNDxabcdVDDxGNDxabcdVDDx(a) Logic graphs for (ab+cd)(b) Euler Paths {abcd}acdxVDDGND(c) stick diagram for ordering {abcd}bEE141CMOS PropertiesFull rail-to-rail swing; high noise marginsLogic levels not dependent upon the relativedevice sizes; ratiolessAlwaysapathtoVddorGndinsteadystate;low output impedanceExtremely high input resistance; nearly zerosteady-state input currentNo direct path steady state between powerand ground; no static power dissipationPropagation delay function of loadcapacitance and resistance of transistors7EE141VTC of Complementary CMOS Gates0.0 1.0Vin, VVout, V2.0 3.00.01.02.03.0A⫽1,B ⫽A⫽B⫽0→1B⫽1, A⫽intBVDDAM3M4ABFM2M10→10→1EE141Body Effect8EE141Switch Delay ModelAReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintEE141Input Pattern Effects on DelayDelay is dependent onthe pattern of inputsLow to high transition» both inputs go low– delay is 0.69 Rp/2 CL» one input goes low– delay is 0.69 RpCLHigh to low transition» both inputs go high– delay is 0.69 2RnCLCLBRnARpBRpARnCint9EE141Delay Dependence on Input Patterns-0.500.511.522.530 100 200 300 400A=B=1→0A=1→0,B=1A=1, B=1→0time [ps]Voltage [V]57A= 1→0, B=176A=1, B=1→035A=B=1→050A= 0→1, B=162A=1, B=0→169A=B=0→1Delay(psec)Input DataPatternNMOS = 0.5µm/0.25 µmPMOS = 0.75µm/0.25 µmCL= 100 fFintBVDDAM3M4ABFM2M1EE141Transistor SizingCLBRnARpBRpARnCintBRpARpARnBRnCLCint10EE141Transistor Sizing a ComplexCMOS GateOUT = D + A • (B + C)DABCDABC12224488661212EE141Fan-In ConsiderationsDCBADCBACLC3C2C1Distributed RC model(Elmore delay)tpHL=0.69Reqn(C1+2C2+3C3+4CL)Propagation delay deterioratesrapidly as a function of fan-in –quadratically in the worst case.11EE141tpas a Function of Fan-IntpLHtp(psec)fan-inGates with afan-ingreater than4 should beavoided.0250500750100012502 4 6 8 10 12 14 16tpHLquadraticlineartpEE141tpas a Function of Fan-Out246810121416tpNOR2tp(psec)eff. fan-outAll gateshave thesame drivecurrent.tpNAND2tpINVSlope is afunction of“drivingstrength”12EE141tpasaFunctionofFan-InandFan-OutFan-in: quadratic due to increasingresistance and capacitanceFan-out: each additional fan-out gateadds two gate capacitances to CLtp=a1FI + a2FI2+a3FOEE141Fast Complex Gates:Design Technique 1Transistor sizing» as long as fan-out capacitance dominatesProgressive sizingInNCLC3C2C1In1In2In3M1M2M3MNDistributed RC lineM1 > M2 > M3 > … >MN(the fet closest to theoutput is the smallest)Can reduce delay by more than20%; decreasing gains astechnology shrinks13EE141Fast Complex Gates:Design Technique 2Transistor orderingC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical path critical pathcharged10→1chargedcharged1delay determined by time todischarge CL,C1and C2delay determined by time todischarge CL110→1chargeddischargeddischargedEE141Fast Complex Gates:Design Technique 3Alternative logic structuresF = ABCDEFGH14EE141Fast Complex Gates:Design Technique 4Isolating fan-in from fan-out using bufferinsertionCLCLEE141Fast Complex Gates:Design Technique 5Reducing the voltage swing» linear reduction in delay» also reduces power consumptionBut the following gate is much slower!Or requires use of “sense amplifiers” on thereceiving end to restore the signal level(memory design)tpHL=0.69(3/4(CLVDD)/ IDSATn)=0.69(3/4(CLVswing)/ IDSATn)15EE141Sizing Logic Paths for SpeedFrequently, input capacitance of a logic pathis constrainedLogic has to drive some capacitanceExample: ALU load in an Intel’smicroprocessor is 0.5pFHowdowesizetheALUdatapathtoachievemaximum speed?We have already solved this for the inverterchain – can we generalize it for any type oflogic?EE141Logical Effort for Inverter ChainCLIn Out12 ND = D1+ D2+ …+ DN++iiiCCDγτ101~∑∑=+=+=NiiiNiiCCTDelay11011~γτHow do we extend thisto any logic network?16EE141Logical Effort+⋅=γτgfpkDelay 0p – parasitic delay - gate parameter ≠ f(W)g – logical effort – gate parameter ≠ f(W)f – electrical effort (effective fanout)Normalize everything to an inverter:ginv=1, pinv=1Everything is measured in unit delays τ0EE141Delay in a Logic GateGate delay:d = h + peffort delayintrinsic delayEffort delay:h = gflogical efforteffective fanout = Cout/CinLogical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size17EE141Buffer Example∑=⋅+=NiiiifgpDelay1γpi, giare constant (and equal to 1)Variables are fiMinimum delay is when fi’s are equal(each stage bears the same effort)CLIn Out12 N(in units of τ0)EE141Logical EffortInverter has the smallest logical effort andintrinsic delay of all static CMOS gatesLogical effort of a gate presents the ratio of itsinput capacitance to the inverter capacitancewhensizedtodeliverthesamecurrentLogical effort increases with the gatecomplexity18EE141Calculating Logical EffortLogical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output currentg =1g =4/3g =5/3EE141Logical Effort of GatesFan-out (f)Normalized delay (d)t1234567pINVtpNANDF(Fan-in)g=1p=1d=f+1g=4/3p=2d=(4/3)f+219EE141Logical EffortEE141Add Branching EffortBranching effort:pathonpathoffpathonCCCb−−−+=20EE141Multistage NetworksStage effort: hi= gifiPath electrical effort: F = Cout/CinPath logical effort: G = g1g2…gNBranching effort: B=b1b2…bNPath effort: H = GFBPath delay D =Σdi= Σpi+
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