EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 17Lecture 17DecodersDecodersRatioedRatioedLogicLogicPassPass--Transistor LogicTransistor LogicEE1412EECS141AnnouncementsAnnouncements Homework #7 due next Tuesday Project phase one in lab next week Project posted Lab reports due this week No lecture/office hour next Tuesday Midterm 3 in two weeks Covering up to next lectureEE1412EE1413EECS141Class MaterialClass Material Last lecture SRAM Register files Today’s lecture Decoders Ratioed logic Pass-transistor logic Reading (Chapters 12, 6)EE1414EECS141Register FileRegister File Schematic very similar to SRAM cell But layout different Sizing different Needs multiple read/write portsEE1413EE1415EECS141Register FileRegister FileBL1WL1BL1BL2BL2WL2Single portTwo-portEE1416EECS141Register fileRegister fileBLWWLWBLRWLREE1414EE1417EECS141DecodersDecodersEE1418EECS141ArrayArray--Structured Memory ArchitectureStructured Memory ArchitectureEE1415EE1419EECS141Memory Architecture: DecodersMemory Architecture: DecodersWord 0Word 1Word 2WordN⫺2WordN⫺1StoragecellMbitsMbitsNwordsS0S1S2SN⫺2A0A1AK⫺1K⫽log2NSN⫺1Word 0Word 1Word 2WordN⫺2WordN⫺1StoragecellS0Input-Output(Mbits)Intuitive architecture for N x M memoryToo many select signals:N words == N select signalsK = log2NDecoder reduces the number of select signalsInput-Output(Mbits)DecoderEE14110EECS141Row DecodersRow DecodersCollection of 2Mcomplex logic gatesOrganized in regular and dense fashion(N)AND DecoderNOR DecoderEE1416EE14111EECS141EE14112EECS141Hierarchical DecodersHierarchical Decoders••••••A2A2A2A3WL0A2A3A2A3A2A3A3A3A0A0A0A1A0A1A0A1A0A1A1A1WL1Multi-stage implementation improves performanceNAND decoder usingNAND decoder using22--input preinput pre--decodersdecodersEE1417EE14113EECS141Project Phase 2Project Phase 2SRAM ArrayWL0WL1WL63a5a4a3a5a4a3a2a1a0EE14114EECS141EE1418EE14115EECS141EE14116EECS141RatioedRatioedLogicLogicEE1419EE14117EECS141RatioedRatioedLogicLogicVDDVSSPDNIn1In2In3FRLLoadVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNResistiveDepletionLoadPMOSLoad(a) resistive load (b) depletion load NMOS (c) pseudo-NMOSVT < 0Goal: to reduce the number of devices over complementary CMOSEE14118EECS141RatioedRatioedLogicLogicVDDVSSPDNIn1In2In3FRLLoadResistiveN transistors + Load• VOH = VDD• VOL = RPNRPN + RL• Assymetrical response• Static power consumption•• tpL= 0.69 RLCLEE14110EE14119EECS141Active LoadsActive LoadsVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNDepletionLoadPMOSLoaddepletion load NMOS pseudo-NMOSVT < 0EE14120EECS141PseudoPseudo--NMOSNMOSVDDABCDFCLVOH = VDD (similar to complementary CMOS)knVDDVTn–()VOLVOL22-------------–⎝⎠⎜⎟⎛⎞kp2------ VDDVTp–()2=VOLVDDVT–()11kpkn------––(assuming that VTVTnVTp)===SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!With long channel devicesEE14111EE14121EECS141PseudoPseudo--NMOS VTCNMOS VTC0.0 0.5 1.0 1.5 2.0 2.50.00.51.01.52.02.53.0Vin[V]Vout[V]W/Lp = 4W/Lp = 2W/Lp = 1W/Lp = 0.25W/Lp = 0.5EE14122EECS141Improved Loads (2)Improved Loads (2)VDDVSSPDN1OutVDDVSSPDN2OutAABBM1 M2Differential Cascode Voltage Switch Logic (DCVSL)EE14112EE14123EECS141EE14124EECS141DCVSL ExampleDCVSL ExampleBAABBBOutOutXOR-NXOR gateEE14113EE14125EECS141DCVSL Transient ResponseDCVSL Transient Response0 0.2 0.4 0.6 0.8 1.0-0.50.51.52.5Time [ns]Vol tage[V]A BA
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