EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 6Lecture 6CMOS InverterCMOS InverterVoltage Transfer CharacteristicVoltage Transfer CharacteristicEE1412EECS141AnnouncementsAnnouncements Lab 2 this week! Lab 3 next week Homework #3 posted, due next Tuesday Prof. Nikolic will not be holding office hours todayEE1413EECS141LabsLabs Monday lab moved to 2-5pmEE1414EECS141Class MaterialClass Material Last lecture MOS transistor operation and modeling Today’s lecture CMOS Inverter: VTC and delay Reading (5.1-5.3, 5.4.2)EE1415EECS141CMOS InverterCMOS InverterVTCVTCEE1416EECS141The CMOS InverterThe CMOS InverterVinVoutVDDEE1412EE1417EECS141VDSpIDpVGSp= -2.5VGSp= -1VDSpIDnVin= 0Vin= 1.5VoutIDnVin= 0Vin= 1.5VoutIDnPMOS Load LinesPMOS Load LinesVin= VDD+ VGSpIDn= -IDpVout= VDD+ VDSpVin= VDD+ VGSpIDn= -IDpVout= VDD+ VDSp Coordinate transform: IDp(VDSp) → IDn(Vout)EE1418EECS141CMOS Inverter Load CharacteristicsCMOS Inverter Load CharacteristicsIDnVoutVin = 2.5Vin = 2Vin = 1.5Vin = 0Vin = 0.5Vin = 1NMOSVin = 0Vin = 0.5Vin = 1Vin = 1.5Vin = 2Vin = 2.5Vin = 1Vin = 1.5PMOSEE1419EECS141CMOS Inverter VTCCMOS Inverter VTCVoutVin0.5 1 1.5 2 2 .50.5 1 1.5 2 2.5NMOS resPMOS offNMOS satPMOS satNMOS offPMOS resNMOS satPMOS resNMOS resPMOS satEE14110EECS141Switching Threshold as a Function Switching Threshold as a Function of Transistor Ratioof Transistor Ratio1001010.80.911.11.21.31.41.51.61.71.8MV(V)Wp/WnEE14111EECS141Determining VDetermining VIHIHand Vand VILILVOHVOLVinVoutVMVILVIHA simplified approachEE14112EECS141Inverter GainInverter Gain0 0.5 1 1.5 2 2.5-18-16-14-12-10-8-6-4-20Vin (V)gainEE1413EE14113EECS141Gain as a function of VDDGain as a function of VDD0 0.05 0.1 0. 15 0.200.050.10.150.2Vin (V)Vout (V)0 0.5 1 1.5 2 2. 500.511.522.5Vin (V)Vout(V)Gain=-1EE14114EECS141Simulated VTCSimulated VTC0 0.5 1 1.5 2 2.500.511.522.5Vin (V)Vout(V)EE14115EECS141Impact of SizingImpact of Sizing0 0.5 1 1.5 2 2.500.511.522.5Vin(V)Vout(V)Wider PMOSWider NMOSSymmetricalEE14116EECS141Impact of Process VariationsImpact of Process Variations0 0.5 1 1.5 2 2.500.511.522.5Vin(V)Vout(V)Fast PMOSSlow NMOSFast NMOSSlow PMOSNominalEE14117EECS141CMOS CMOS SwitchingSwitchingEE14118EECS141MOS Transistor as a Switch MOS Transistor as a Switch Discharging a capacitor•Can solve:()DSDDvii=dtdVCiDSD=CEE1414EE14119EECS141MOS Transistor as a SwitchMOS Transistor as a SwitchTraversed pathIDVDSVDDVDD /2VGS = VDDRmidR0∫∫⋅−=⋅−===2112211221)()(1)(1))((ttDDSttontttoneqdttItVttdttRtttRavgR())()(2121tRtRRononeq+⋅≈VGS≥ VTSDRonEE14120EECS141The Transistor as a SwitchThe Transistor as a SwitchVGS≥ VTSDRon()()⎟⎟⎠⎞⎜⎜⎝⎛⋅λ+⋅+⋅λ+⋅⋅=212121DDDSATDDDDDSATDDeqVIVVIVR⎟⎠⎞⎜⎝⎛⋅λ⋅−⋅≈DDDSATDDeqVIVR65143IDVDSVDDVDD /2VGS = VDDRmidR0()mideqRRR +⋅=021EE14121EECS141MOS Transistor as a SwitchMOS Transistor as a SwitchSolving the integral:Averaging resistances:DSATDDeqIVR ⋅≈43Often just:EE14122EECS141The Transistor as a SwitchThe Transistor as a Switch0.5 1 1.5 2 2.501234567x 105VDD (V)Req (Ohm )EE14123EECS141The Transistor as a SwitchThe Transistor as a SwitchEE14124EECS141MOS CapacitancesMOS CapacitancesDynamic BehaviorDynamic BehaviorEE1415EE14125EECS141CGDCGSCSBCDBCGB(Miller)MOS CapacitancesMOS Capacitances= CGCS+ CGSO= CGCD+ CGDO= CGCB= CdiffGSDB= CdiffEE14126EECS141GateGate--Channel CapacitanceChannel CapacitanceSDGCGCSDGCGCSDGCGCCut-off Resistive SaturationOff/Lin Æ Cgate= Cox·W·LeffTextbook: page 109CGCBCGCSCGCDSat Æ Cgate= (2/3)·Cox·W·LeffoxoxoxtCε=EE14127EECS141Gate Overlap CapacitanceGate Overlap CapacitancedoxOxCC ⋅=xdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WxdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WOff/Lin/Sat Æ CGSO= CGDO= CO·Wtoxn+n+Cross sectionLGate oxidetoxn+n+Cross sectionLGate oxideEE14128EECS141Diffusion CapacitanceDiffusion CapacitanceBottomSide wallSide wallChannelSourceSubstrateWNA+NALSNDxjCdiff= Cbottom+ Csw= Cj· AREA + Cjsw· PERIMETEROff/Lin/Sat Æ Cdiff= Cj·LS·W + Cjsw·(2LS+W)EE14129EECS141Capacitive Device ModelCapacitive Device Model Gate-Channel Capacitance CGC= Cox·W·Leff(Off, Linear) CGC= (2/3)·Cox·W·Leff(Saturation) Gate Overlap Capacitance CGSO= CGDO= CO·W (Always) Junction/Diffusion Capacitance Cdiff= Cj·LS·W + Cjsw·(2LS+ W) (Always)EE14130EECS141The Miller EffectThe Miller EffectVinM1Cgd1VoutΔVΔVVinM1VoutΔVΔV2Cgd1“A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.”EE1416EE14131EECS141LinearizingLinearizingthe Junction Capacitancethe Junction CapacitanceReplace non-linear capacitance bylarge-signal equivalent linear capacitancewhich displaces equal charge over voltage swing of interestEE14132EECS141FanoutVoutVinCLSimplifiedModelM3M4M1M 2CwCg3Cdb1Cg4Vout2Cdb2VDDVDDVinVoutCgd12Computing the CapacitancesComputing the Capacitances123Miller effectReverse biased junctionOff Æ Sat (M4)Lin (M3)4No Miller effectEE14133EECS141Computing the CapacitancesComputing the CapacitancesVDDEE14134EECS141Computing the CapacitancesComputing the CapacitancesMiller effect(Off Æ Sat*)(Lin*)* assuming LH transition at VoutReverse biased junction123EE14135EECS141Capacitances in 0.25 Capacitances in 0.25 μμm CMOS m CMOS ProcessProcessIn most CMOS processes (in any technology)Cg~ Cd~ 1.5 – 2fF/µm (width)EE14136EECS141.MODEL Parameters MOS Level 1.MODEL Parameters MOS Level 1 .MODEL Modname NMOS/PMOS <VTO=VTO...>EE1417EE14137EECS141Next LectureNext Lecture Propagation
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