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Berkeley ELENG 141 - Lecture 13 CMOS Logic Review

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EE1411EECS1411Lecture #13EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 13Lecture 13CMOS Logic ReviewCMOS Logic ReviewEE1412EECS1412Lecture #13AnnouncementsAnnouncements Lab #5 tomorrow, next Mon. and Tues. Homework #6 out today, due next Thurs. Reminder: Project coming up in 2 weeks – find a partnerEE1413EECS1413Lecture #13Class MaterialClass Material Last lecture CMOS Delay and Power Models Today’s lecture CMOS Logic Review Reading (6)EE1414EECS1414Lecture #13CMOS Logic CMOS Logic ReviewReviewEE1415EECS1415Lecture #13Cell DesignCell Design Standard Cells General purpose logic Used to synthesize RTL/HDL Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cellEE1416EECS1416Lecture #13Standard Cell Layout Methodology Standard Cell Layout Methodology ––1980s1980ssignalsRoutingchannelVDDGNDEE1417EECS1417Lecture #13Standard Cell Layout Methodology Standard Cell Layout Methodology ––1990s 1990s --TodayTodayM2No routingchannelsVDDGNDM3VDDGNDMirrored CellMirrored CellEE1418EECS1418Lecture #13Standard CellsStandard CellsCell boundaryN WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objectsCell height is “12 Mn pitch”2λRails ~10λInOutVDDGNDEE1419EECS1419Lecture #13Standard CellsStandard CellsInOutVDDGNDIn OutVDDGNDWith silicideddiffusionWith minimaldiffusionroutingOutInVDDM2M1EE14110EECS14110Lecture #13Standard CellsStandard CellsAOutVDDGNDB2-input NAND gateBVDDAEE14111EECS14111Lecture #13Stick DiagramsStick DiagramsContains no dimensionsRepresents relative positions of transistorsInOutVDDGNDInverterAOutVDDGNDBNAND2EE14112EECS14112Lecture #13Stick DiagramsStick DiagramsCABX = C • (A + B)BACijVDDXXiGNDABCPUNPDNABCLogic GraphjEE14113EECS14113Lecture #13Two Versions of C Two Versions of C ••(A + B)(A + B)XCAB ABCXVDDGNDVDDGNDEE14114EECS14114Lecture #13Consistent Euler PathConsistent Euler PathjVDDXXiGNDABCABCHas PDN and PUPABCHas PUP, but no PDNEE14115EECS14115Lecture #13OAI22 Logic GraphOAI22 Logic GraphCABX = (A+B)•(C+D)BADVDDXXGNDABCPUNPDNCDDABCDEE14116EECS14116Lecture #13Example: x = Example: x = ab+cdab+cdGNDxabcdVDDxGNDxabcdVDDx(a) Logic graphs for (ab+cd)(b) Euler Paths {a b c d}acdxVDDGND(c) stick diagram for ordering {a b c d}bEE14117EECS14117Lecture #13MultiMulti--Fingered TransistorsFingered TransistorsOne fingerTwo fingers (folded)Less diffusion capacitanceEE14118EECS14118Lecture #13FanFan--In ConsiderationsIn ConsiderationsDCBAD: 0Æ1C: 1B: 1A: 1CLC3C2C1RC model:22224444EE14119EECS14119Lecture #13FanFan--In ConsiderationsIn ConsiderationsDCBADCBACLC3C2C1Distributed RC model(Elmore delay)tpHL= 0.69 Reqn(C1+2C2+3C3+4CL)Propagation delay deteriorates rapidly as a function of fan-in –quadratically in the worst case.22224444EE14120EECS14120Lecture #13ttppas a Function of Fanas a Function of Fan--InIntp(psec)fan-inGates with a fan-in greater than 4 should be avoided.0250500750100012502 4 6 8 10 12 14 16tpHLquadraticlineartptpLHEE14121EECS14121Lecture #13Reducing Parasitic Delay (1)Reducing Parasitic Delay (1) Transistor sizing as long as fan-out capacitance dominates Progressive sizingInNCLC3C2C1In1In2In3M1M2M3MNDistributed RC lineM1 > M2 > M3 > … > MN(the FET closest to theoutput is the smallest)Can reduce delay by more than 20%; Be careful: input loading, junction caps, decreasing gains as technology shrinksEE14122EECS14122Lecture #13Impact on Logical EffortImpact on Logical EffortEE14123EECS14123Lecture #13Reducing Parasitic Delay (2)Reducing Parasitic Delay (2) Transistor orderingC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical path critical pathcharged10→1chargedcharged1delay determined by time to discharge CL, C1and C2delay determined by time to discharge CL110→1chargeddischargeddischargedEE14124EECS14124Lecture #13Reducing Delay (3)Reducing Delay (3) Reducing the voltage swing linear reduction in delay also reduces power consumption But the following gate is slower! Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design)tpHL= 0.5 (CL VDD) / IDSATn= 0.5 (CL Vswing) / IDSATnEE14125EECS14125Lecture #13LE in Modern ProcessesLE in Modern ProcessesEE14126EECS14126Lecture #13LE in Modern ProcessesLE in Modern ProcessesEE14127EECS14127Lecture #13Next LectureNext Lecture


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Berkeley ELENG 141 - Lecture 13 CMOS Logic Review

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