EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 11Lecture 11Wire modelingWire modelingCMOS logicCMOS logicEE1412EECS141AnnouncementsAnnouncements No lab this week Lab 4 reports due next week Hardware lab next week No new homework this week Midterm 1 tonight, 6:30-8pm, 105 North G. Material until lecture 10, homework 5, lab 4 No lecture on October 24EE1413EECS141Class MaterialClass Material Last lecture Wire models Today’s lecture CMOS logic gates Reading (Chapter 6)EE1414EECS141CMOS LogicCMOS LogicEE1415EECS141Combinational vs. Sequential LogicCombinational vs. Sequential LogicCombinational SequentialOutput = f(In)Output = f(In, Previous In)CombinationalLogicCircuitOutInCombinationalLogicCircuitOutInStateEE1416EECS141Static CMOS CircuitStatic CMOS CircuitAt every point in time (except during the switching transients) each gate output is connected to eitherVDDorVssvia a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit style, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.EE1412EE1417EECS141Static Complementary CMOSStatic Complementary CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPMOS onlyNMOS onlyPUN and PDN are dual logic networksPUN and PDN functions are complementary ……EE1418EECS141NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel ConnectionY = X if A AND BY = X if A OR B Transistor ↔ switch controlled by its gate signal NMOS switch closes when switch control input is high NMOS transistors pass a “strong” 0 but a “weak” 1ABXYXYABAND OR EE1419EECS141PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection PMOS switch closes when switch control is low PMOS transistors pass a “strong” 1 but a “weak” 0XYABABXYNOR NAND Y = X if A AND B = A + BY = X if A OR B = ABEE14110EECS141Threshold DropsThreshold DropsVDDVDD→ 0PDN0 → VDDCLCLPUNVDD0 → VDD-VTnCLVDDVDDVDD→ |VTp|CLSDSDVGSSSDDVGSEE14111EECS141Complementary CMOS Logic StyleComplementary CMOS Logic Style PUP is the dual to PDN(can be shown using DeMorgan’s Theorems) The complementary gate is invertingA + B = ABAB = A + BAND = NAND + INVEE14112EECS141Example Gate: NANDExample Gate: NAND PDN: G = AB ⇒ Conduction to GND PUN: F = A + B = AB ⇒ Conduction to VDD G(In1,In2,In3,…) ≡ F(In1,In2,In3,…)EE1413EE14113EECS141Example Gate: NORExample Gate: NOREE14114EECS141Complex CMOS GateComplex CMOS GateOUT = D + A • (B + C)DABCDABCEE14115EECS141Constructing a Complex GateConstructing a Complex GateC(a) pull-down networkSN1SN4SN2SN3DFFADBCDFABC(b) Deriving the pull-up networkhierarchically by identifyingsub-netsDAABCVDDVDDB(c) complete gateEE14116EECS141Cell DesignCell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and widthEE14117EECS141Standard Cell Layout Methodology Standard Cell Layout Methodology ––1980s1980ssignalsRoutingchannelVDDGNDEE14118EECS141Standard Cell Layout Methodology Standard Cell Layout Methodology ––1990s 1990s --TodayTodayM2No routingchannelsVDDGNDM3VDDGNDMirrored CellMirrored CellEE1414EE14119EECS141Standard CellsStandard CellsCell boundaryN WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objectsCell height is “12 Mn pitch”2λRails ~10λInOutVDDGNDEE14120EECS141Standard CellsStandard CellsInOutVDDGNDIn OutVDDGNDWith silicideddiffusionWith minimaldiffusionroutingOutInVDDM2M1EE14121EECS141Standard CellsStandard CellsAOutVDDGNDB2-input NAND gateBVDDAEE14122EECS141Stick DiagramsStick DiagramsContains no dimensionsRepresents relative positions of transistorsInOutVDDGNDInverterAOutVDDGNDBNAND2EE14123EECS141Stick DiagramsStick DiagramsCABX = C • (A + B)BACijjVDDXXiGNDABCPUNPDNABCLogic GraphEE14124EECS141Two Versions of C Two Versions of C ••(A + B)(A + B)XCAB ABCXVDDGNDVDDGNDEE1415EE14125EECS141Consistent Euler PathConsistent Euler PathjVDDXXiGNDABCABCEE14126EECS141OAI22 Logic GraphOAI22 Logic GraphCABX = (A+B)•(C+D)BADVDDXXGNDABCPUNPDNCDDABCDEE14127EECS141Example: x = Example: x = ab+cdab+cdGNDxabcdVDDxGNDxabcdVDDx(a) Logic graphs for (ab+cd)(b) Euler Paths {a b c d}acdxVDDGND(c) stick diagram for ordering {a b c d}bEE14128EECS141MultiMulti--Fingered TransistorsFingered TransistorsOne fingerTwo fingers (folded)Less diffusion capacitanceEE14129EECS141CMOS PropertiesCMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistorsEE14130EECS141Next LectureNext Lecture CMOS logic -
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