EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 22Lecture 22Sequential LogicSequential LogicEE1412EECS141AnnouncementsAnnouncements Homework 8 due next Thursday Project phase two in lab this week Friday is a holiday Makeup lab today, 3pm Phase 2 reports due on Monday Phase 3 next weekEE1412EE1413EECS141Class MaterialClass Material Last lecture Finished domino logic Revisited power Today’s lecture Sequential logic Reading Chapter 7EE1414EECS141Sequential Sequential LogicLogicEE1413EE1415EECS141Writing into a Static LatchWriting into a Static LatchCLKCLKCLKDQDCLKCLKQConverting into a MUX (gated feedback)Forcing the state(can implement as NMOS-only)Use the clock as a decoupling signal, that distinguishes between the transparent and opaque statesEE1416EECS141Latch PropertiesLatch Properties Two phase operation Clk = 1: transparent Clk = 0: latches data Transparency can cause the data contamination Often avoided by using edge-triggered registersCLKCLKCLKDQEE1414EE1417EECS141MasterMaster--Slave (EdgeSlave (Edge--Triggered) Triggered) RegisterRegister10DCLKQMMaster01CLKQSlaveQMQDCLKTwo opposite latches trigger on edgeAlso called master-slave latch pair EE1418EECS141MasterMaster--Slave RegisterSlave RegisterQMQDCLKT2I2T1I1I3T4I5T3I4I6Multiplexer-based latch pairEE1415EE1419EECS141Reduced Clock Load Reduced Clock Load MasterMaster--Slave RegisterSlave RegisterDQT1I1CLKCLKT2CLKCLKI2I3I4EE14110EECS141ClkClk--Q DelayQ DelayDQCLK⫺0.50.51.52.5tc ⫺ q(lh)0.5 1 1.5 2 2.50time, nsecVoltstc ⫺ q(hl)EE1416EE14111EECS141Setup TimeSetup TimeDQQMCLKI2⫺ T2⫺0.5Volts0.00.2 0.4time (nsec)(a) Tsetup⫽ 0.21 nsec0.6 0.8 100.51.01.52.02.53.0DQQMCLKI2⫺ T2⫺0.5Volts0.00.2 0.4time (nsec)(b) Tsetup⫽ 0.20 nsec0.6 0.8 100.51.01.52.02.53.0EE14112EECS141More Precise Setup TimeMore Precise Setup TimetD ⫺ CttttC ⫺ Q1.05tC ⫺ QtSutHClkDQ(b)(a)EE1417EE14113EECS141Clk-Q DelayTSetup-1TClk-QTimeSetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)DCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1EE14114EECS141Clk-Q DelayTSetup-1TClk-QTimeTimet=0ClockDataTSetup-1SetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)DCNQMCPD1SMInv1Inv2TG1EE1418EE14115EECS141Clk-Q DelayTSetup-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1SetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)EE14116EECS141Clk-Q DelayTSetup-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1SetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)EE1419EE14117EECS141Timet=0ClockDataTSetup-1DCNQMCPD1SMInv1Inv2TG1SetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)Clk-Q DelayTSetup-1TClk-QTimeEE14118EECS141SetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 caseDCNQMCPD1SMInv1Inv2TG1Timet=0DataClockTHold-10Clk-Q DelayTHold-1TClk-QTimeEE14110EE14119EECS141Clk-Q DelayTHold-1TClk-QTimeTimet=0DataClockTHold-1SetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 caseDCNQMCPD1SMInv1Inv2TG10EE14120EECS141Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0DataClockTHold-1SetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 case0EE14111EE14121EECS141Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockTHold-1DataSetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 case0EE14122EECS141Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockTHold-1DataSetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 case0⇒EE14112EE14123EECS141Other Latches/Registers: COther Latches/Registers: C22MOSMOSM1DQM3CLKM4M2CLKVDDCL1XCL2Master StageM5M7CLKCLKM8M6VDDSlave StageKeepers should be added to staticizeEE14124EECS141Other Latches/Registers: TSPCOther Latches/Registers: TSPCCLKInVDDCLKVDDInOutCLKVDDCLKVDDOutNegative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)EE14113EE14125EECS141Including Logic in TSPCIncluding Logic in TSPCCLKIn CLKVDDVDDQPUNPDNCLKVDDQCLKVDDIn1In1In2In2AND latchExample: logic inside the latchEE14126EECS141TSPC RegisterTSPC RegisterCLKCLKDVDDM3M2M1CLKYVDDQQM9M8M7CLKXVDDM6M5M4EE14114EE14127EECS141PulsePulse--Triggered LatchesTriggered LatchesMaster-Slave LatchesDClkQ DClkQClkDataDClkQClkDataPulse-Triggered LatchL1 L2 LWays to design an edge-triggered sequential cell:EE14128EECS141Pulsed LatchesPulsed LatchesCLKGDVDDM3M2M1CLKGVDDM6QM5M4CLKCLKGVDDXMPMN(a) register (b) glitch generationCLKCLKG(c) glitch clockEE14115EE14129EECS141Pulsed LatchesPulsed LatchesHybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :P1M3M2DCLKM1P3M6QxM5M4P2CLKDEE14130EECS141HLFF TimingHLFF Timing20.50.00.51.01.52.02.53.00.20.0 0.4QDtime (ns)Volts0.6 0.8 1.0CLKDCLKEE14116EE14131EECS141Other Other Sequential Sequential CircuitsCircuitsEE14132EECS141Other Sequential CircuitsOther Sequential Circuits Schmitt Trigger Monostable Multivibrators Astable MultivibratorsEE14117EE14133EECS141Schmitt TriggerSchmitt TriggerIn OutVinVou tVOHVOLVM–VM+•VTC with hysteresis•Restores signal slopesEE14134EECS141Noise Suppression using Schmitt TriggerNoise Suppression using Schmitt TriggerEE14118EE14135EECS141CMOS Schmitt TriggerCMOS Schmitt TriggerMoves switching thresholdof the first inverter VinM2M1VDDXVoutM4M3EE14136EECS1412.5VX(V)VM2VM1Vin(V)VCT with hysteresis2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.52.5Vx(V)k= 2k= 3k= 4k= 1Vin(V)2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.5The effect of varying the ratio of the PMOS device M4. The width is k*0.5μm.Schmitt Trigger: Simulated VTCSchmitt Trigger: Simulated VTCEE14119EE14137EECS141CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)VDDVDDOutInM1M5M2XM3M4M6EE14138EECS141Bistable MultivibratorMonostable MultivibratorAstable Multivibratorflip-flop, Schmitt Triggerone-shotoscillatorSRTMultivibratorMultivibratorCircuitsCircuitsEE14120EE14139EECS141DELAYtdInOuttdTransitionTransition--Triggered MonostableTriggered MonostableEE14140EECS141VDDInOutABCRInBOuttVMt2t1(a) Trigger circuit.(b) Waveforms.Monostable Triggered (RCMonostable Triggered (RC--based)based)EE14121EE14141EECS141Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)012 N-1simulated response of 5-stage oscillatorEE14142EECS141Next LectureNext Lecture Sequential logic
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