DOC PREVIEW
Berkeley ELENG 141 - Lecture 9 CMOS scaling Introduction to wires

This preview shows page 1-2-3 out of 10 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

EE1411EE1411EECS141-S04EE141EE141--Spring 2004Spring 2004Digital Integrated Digital Integrated CircuitsCircuitsLecture 9Lecture 9CMOS scalingCMOS scalingIntroduction to wiresIntroduction to wiresEE1412EECS141-S04Administrative StuffAdministrative Stuff Office hours today: 4-5:30pm (511 Cory) Lab 4 this week – Mo lab to be made up next week Brian’s discussion session and OH this week: Discussion: We 10-11am in 353 Cory OH: 5-6pm in 353 Cory Homework #4 due 2/19 Midterm 1 is next Thursday,Febr 26, 6:30-8pm 277 Cory Review session Febr 25, 6-7:30pm TBD Material up to Lecture 9 (Scaling) – Ch 1, Ch2 (partial), Ch 3 (partial), Ch4 Open book, open notes No labs next week No new homework next week Past midterms posted on the webEE1413EECS141-S04Last LectureLast Lecture Last lecture Buffer sizing Power dissipation Today’s lecture CMOS scaling Introduction to wiresEE1414EECS141-S04Impact ofImpact ofTechnology ScalingTechnology ScalingEE1412EE1415EECS141-S04Goals of Technology ScalingGoals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a transistor has to be reduced But also want to be faster, smaller, lower powerEE1416EECS141-S04Technology ScalingTechnology Scaling Technology generation spans 2-3 years Benefits of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency Die size used to increase by 14% per generationEE1417EECS141-S04Technology GenerationsTechnology GenerationsEE1418EECS141-S04Technology RoadmapTechnology RoadmapInternational Technology Roadmap for Semiconductors2002 dataNode years: 2007/65nm, 2010/45nm, 2013/32nm, 2016/22nmYear 2001 2003 2005 2007 2010 2013 2016 DRAM ½ pitch [nm] 130 100 80 65 45 32 22 MPU transistors/chip 97M 153M 243M 386M 773M 1.55G 3.09G Wiring levels 8 8 10 10 10 11 11 High-perf. phys. gate [nm] 65 45 32 25 18 13 9 High-perf. VDD [V] 1.2 1.0 0.9 0.7 0.6 0.5 0.4 Local clock [GHz] 1.7 3.1 5.2 6.7 11.5 19.3 28.8 High-perf. power [W] 130 150 170 190 218 251 288 Low-power phys. gate [nm] 90 65 45 32 22 16 11 Low-power VDD [V] 1.2 1.1 1.0 0.9 0.8 0.7 0.6 Low-power power [W] 2.4 2.8 3.2 3.5 3.0 3.0 3.0EE1413EE1419EECS141-S04ITRS Technology Roadmap ITRS Technology Roadmap Acceleration ContinuesAcceleration ContinuesEE14110EECS141-S04Technology Scaling (1)Technology Scaling (1)Minimum Feature SizeMinimum Feature Size1960 1970 1980 1990 2000 201010-210-1100101102YearMinimum Feature Size (micron)EE14111EECS141-S04Technology Scaling (2) Technology Scaling (2) Number of components per chipNumber of components per chipEE14112EECS141-S04Technology Scaling (3)Technology Scaling (3)Propagation DelayPropagation Delaytpdecreases by 30%/yearf increases by 43%EE1414EE14113EECS141-S04Technology Scaling (4)Technology Scaling (4)(a) Power dissipation vs. year.959085800.010.1110100YearPower Dissipation (W)x4 / 3 yearsMPU DSPx1.4 / 3 yearsScaling Factor κ (normalized by 4µm design rule)1011101001000∝ κ 3Power Density (mW/mm2)∝ κ 0.7(b) Power density vs. scaling factor.From KurodaEE14114EECS141-S04Technology Scaling Models Technology Scaling Models • Full Scaling (Constant Electrical Field)• Fixed Voltage Scaling• General Scalingideal model — dimensions and voltage scaletogether by the same factor Smost common model until recently —only dimensions scale, voltages remain constantmost realistic for todays situation —voltages and dimensions scale with different factorsEE14115EECS141-S04Scaling Relationships for Long Channel DevicesScaling Relationships for Long Channel DevicesEE14116EECS141-S04Transistor ScalingTransistor Scaling(Velocity(Velocity--Saturated Devices)Saturated Devices)EE1415EE14117EECS141-S04µµProcessorProcessorScalingScalingS. Borkar, IEEE Micro 1999.P.Gelsinger: µProcessors for the New Millenium, ISSCC 200140048008808080858086286386486Pentium® procP60.0010.010.111010010001970 1980 1990 2000 2010YearTransistors (MT)2X growth in 1.96 years!EE14118EECS141-S04µµProcessorProcessorPowerPowerS. Borkar, IEEE Micro 1999.P.Gelsinger: µProcessors for the New Millenium, ISSCC 20015KW 18KW 1.5KW 500W 40048008808080858086286386486Pentium® proc0.11101001000100001000001971 1974 1978 1985 1992 2000 2004 2008YearPower (Watts)EE14119EECS141-S04µµProcessorProcessorPerformancePerformanceP.Gelsinger: µProcessors for the New Millenium, ISSCC 2001EE14120EECS141-S042010 Outlook2010 Outlook Performance 2X/16 months 1 TIP (terra instructions/s) 30 GHz clock Size No of transistors: 2 Billion Die: 40*40 mm Power 10kW!! Leakage: 1/3 of total PowerP.Gelsinger: µProcessors for the New Millenium, ISSCC 2001EE1416EE14121EECS141-S04Some interesting questionsSome interesting questions What will cause this model to break? When will it break? Will the model gradually slow down? Power and power density Leakage Process VariationEE14122EECS141-S04WiresWiresEE14123EECS141-S04The WireThe Wiretransm ittersreceiversschematicsphysicalEE14124EECS141-S04Interconnect Impact on ChipInterconnect Impact on ChipEE1417EE14125EECS141-S04Wire ModelsWire ModelsAll-inclusive modelCapacitance-onlyEE14126EECS141-S04Impact of Interconnect Impact of Interconnect ParasiticsParasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive InductiveEE14127EECS141-S0410 100 1,000 10,000 100,000Length (u)No of nets(Log Scale)Pentium Pro (R)Pentium(R) IIPentium (MMX)Pentium (R)Pentium (R) IINature of InterconnectNature of InterconnectLocal InterconnectGlobal InterconnectSLocal = STechnologySGlobal= SDieSource: IntelEE14128EECS141-S04INTERCONNECTINTERCONNECTEE1418EE14129EECS141-S04Capacitance of Wire InterconnectCapacitance of Wire InterconnectVDDVDDVinVoutM1M2M3M4Cdb2Cdb1Cgd12CwCg4Cg3Vout2FanoutInterconnectVoutVinCLSimplifiedModelEE14130EECS141-S04Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate ModelDiele ctricSubstrateLWHtdiElectrical-field linesCurre nt flowWLtcdidiintε=LLCwireSSSSS1=⋅=EE14131EECS141-S04PermittivityPermittivityEE14132EECS141-S04Fringing CapacitanceFringing CapacitanceW -


View Full Document

Berkeley ELENG 141 - Lecture 9 CMOS scaling Introduction to wires

Documents in this Course
Adders

Adders

7 pages

Memory

Memory

33 pages

I/O

I/O

14 pages

Lecture 8

Lecture 8

34 pages

Lab 3

Lab 3

2 pages

I/O

I/O

17 pages

Project

Project

6 pages

Adders

Adders

15 pages

SRAM

SRAM

13 pages

Load more
Download Lecture 9 CMOS scaling Introduction to wires
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lecture 9 CMOS scaling Introduction to wires and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 9 CMOS scaling Introduction to wires 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?