Prof. Jan Rabaey EECS 141Project 1Due Thursday, March 20th, 5pm @ 558 CoryUNIVERSITY OF CALIFORNIACollege of EngineeringDepartment of Electrical Engineering and Computer SciencesProf. Jan Rabaey EECS 141Spring 2003Project 1Due Thursday, March 20th, 5pm @ 558 CoryName (Last, First) Student ID Design GroupScoreboardPhase-1Phase-2Phase-3Total (pts)EECS141: SPRING 03—PROJECT 1 1Background InformationYou are given technology parameters that are essential in propagation delay analysis. Theseparameters are extracted by curve fitting simulated results of an inverter delay in our 0.25mtechnology, as shown in Fig. 1.Figure 1: Extraction of delay parameters: (a) tp0, , (b) Von, d.(Wp/Wn=2/1L=0.25)All parameters are extracted using the same test circuit as that given in Hw 5/Prob 4. (on a sidenote, values of tp0 and shown in Fig. 1 is the solution to this homework problem!) Parameterstp0 and will aid in calculation of the gate delay as given by:01p pft tg� �= � +� �� �(1)where tp0 is the intrinsic delay of an inverter, f is the fanout, and = Cintrinsic/Cgate is the ratio of theinput intrinsic to the input gate capacitance.Parameters Von and d are intrinsically related, but not equal to the transistor thresholdvoltage and velocity saturation index. They are simply fitting parameters that provide the mostaccurate model of a FO4 inverter delay over a range of supply voltages. Fanout of four is chosenfor calibration simply because it is the most typical fanout found in well-designed digital circuits.It also represents good average fanout, so we will use the same parameters for all other fanoutsthat we are going to encounter in this design project. Relationship between the propagation delayof a FO4 inverter and the power supply Vdd is given by: ( )dddp ddd onVt KV Va= �-(2)where Kd is another fitting parameter, but it is not crucial for our problem setup. It lumps sometechnology parameters including linearized delay capacitance (similar to the one you had todetermine in Hw 4/Prob 4). You will find equation (2) useful in Vdd-based optimizations.EECS141: SPRING 03—PROJECT 1 2Phase 1: Circuit Optimization (1 week)You have to optimize circuit given in Fig. 2:b1=2 b2=4128x5x21x3x4Figure 2: Some group-specific inverter-based topology.First, find sizes x2-x5 of all gates to achieve minimum delay Dmin from the input to output.What is the value of Dmin normalized to tp0? What is the energy Eref that corresponds to theminimum delay? For energy calculation, assume VDD = VDDnom = 2.5V. Express Eref in terms ofenergy required to drive the input gate capacitance Cgate = 1 (call this number “1”, it is simply areference case, you do not need value in fF in your calculations) of the first gate in the chain.Now, you obtained reference point (Dmin, Eref) for your optimizations.Assume now that you have to increase delay by x%. For the newly specified delay, performfollowing three optimizations in order to minimize total energy of the reference design.a) Gate size (W) optimizationWhat are the new sizes of all the gates x2-x5?What is the achieved percent energy reduction, ERW = 100(1 – EW/Eref)?b) Supply voltage (Vdd) optimizationWhat is the value of the new supply voltage, VDDopt?What is the achieved percent energy reduction, ERVdd = 100(1 – EVdd/Eref)?c) Combined size and supply voltage (W-Vdd) optimizationWhat are the new sizes of all the gates x2-x5?What is the value of the new supply voltage, VDDopt?What is the achieved percent energy reduction, ERW-Vdd = 100(1 – EW-Vdd/Eref)?Clearly show your design methodology and summarize all results in following Table:Summary of results from Phase-1: Dmin (tp0) = Eref =Opt. case ER (%) VDDoptx2x3x4x5Reference 0% 2.5VW 2.5VVddW-VddEECS141: SPRING 03—PROJECT 1 3Phase 2: Verification in HSPICE (1/2 week)Using HSPICE, verify results of your optimizations from Phase-1.a) Obtain reference point (Dmin, Eref) in HSPICE. Is it different from what you expected?(Hint-1: CD and CE from Prob 4/Hw 4 could help, but don’t blame everything on them!)(Hint-2: To determine energy dissipated in driving the input gate capacitance in HSPICEverification, you may want to use some of the results from background section and/or useHSPICE to estimate this energy)b) Using parameters (gate size, VDDopt) from Phase-1, report achieved delay increase DI andachieved energy reduction ER for all three optimization cases. Normalize numbersrelative to the reference case (Dmin, Eref) obtained by HSPICE in part (a) of Phase-2.Comment your results.Summary of results from Phase-2:ReferenceDmin (ps) Eref (Ein-1st stage)HSPICE Phase-1 HSPICE Phase-1VerificationER (%) DI (%)HSPICE Phase-1 HSPICE Phase-1W x%Vdd x%W-Vdd x%Phase 3: MAX Layout (1/2 week)Layout the last three stages of circuit in Fig. 2 when sized for Dmin. Do not layout branchinggate at the output of the 4th stage. The objective is to minimize area and achieve aspect ratio asclose to 1 as possible. Report following numbers (layout must be DRC-error-free!):a) Total layout areab) Layout aspect ratioSummary of results from Phase-3:Total layout area(m2)Aspect ratioEECS141: SPRING 03—PROJECT 1
View Full Document
Unlocking...