UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 EECS141 Due Thursday, Oct. 23 @ 240 Cory Problem 1: Complex CMOS Gates a) Implement the function . Assuming long-channel transistors, size the devices so that the drive resistance is the same as an inverter with WN/L =2 and WP/L =4. b) Imagine that input "A" to the gate was always the last one to arrive, making the delay of the gate from A rising or falling to the output falling or rising critical. Please re-arrange the implementation of your gate so that the delay of the gate from A transitioning is minimized. c) Re-arrange your gate once again, but this time to minimize the delay of the gate for "D" being the critical input. d) Draw a stick diagram of the gate you designed for part c) - you should minimize the diffusion breaks and use a single piece of poly for each input. Problem 2: Wires and Tapering Use Tables 4-2 and 4-3 from the book for this problem. Also, assume that the sheet resistance of an aluminum wire is .075Ώ/□. a) For an aluminum wire of width 0.24µm on the first layer of metal (Al1) that does not run over any active area and has no other wires above, below, or around it, what is the total capacitance per unit length? What is the resistance per unit length? b) How long does this same wire need to be for its step input RC delay to be 100ps? c) If the same 0.24µm wide wire now had two wires on the same layer running parallel to it (with minimum spacing), assuming the parallel wires are both connected to one of the rails, what is the new capacitance per unit length? Figure 1 d) The wire shown in Figure 1 is on the third metal layer (Al3) and it does not run over any active area. There are no wires close to it and the load attached to the end of the wire has half the capacitance of the first wire section (the one with size). Assume L = 100 um, W= 0.7 um, and S= 0.7. Ignoring fringing capacitance, draw the RC model you would use to calculate the delay of this wire. Using this model, what is the step input RC delay of the wire?e) BONUS: What is the optimal tapering factor (S) that minimizes the delay of the wire? Problem 3: Repeaters For this problem, use the following parameters for the wire: R = 0.075 Ώ/□, W = .1 um, and C = 0.2 fF/um (this number includes the effects of both parallel plate and fringe capacitance). For the inverters you should assume that Vdd = 1.2V, Cg = 2 fF/um, Cd = 1 fF/um, Rnmos = 10 kΏ/□, and Rpmos = 20 kΏ/□. All of the inverters in Figure 2 are the same size as the first inverter. Figure 2 a) Draw an RC model for the above circuit and calculate the delay from the input to Vout. You should include slope effect, but you can assume that the input is driven by another circuit with the same delay as first inverter, and that ln(2)*(1+VT*/Vdd)=1. In other words, you can approximate the Elmore delay as being equal to just RC (instead of ln(2)*RC). b) Now assume you have a wire with a total length of L and that this wire is broken into N repeated sections with identically sized inverters (where each inverter is a factor of S bigger than the inverters shown in Figure 2). How does delay depend on N, inverter sizing S, and wire length L? c) What N and S minimize the delay for a given
View Full Document
Unlocking...