EECS 141: FALL 2005—FINAL 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-12:30 Thursday, December 15, 5:00-8:00pm EECS 141: FALL 2005—FINAL NAME SOLUTION Last First SID Problem 1 (7): 7 Problem 2 (9): 9 Problem 3 (15): 15 Problem 4 (11): 11 Problem 5 (10): 10 Problem 6 (8): 8 Problem 7 (15): 15 Total (75) 75EECS 141: FALL 2005—FINAL 2PROBLEM 1: Devices (7 pts) Consider the inverter shown below. In OutVDD Compared to an inverter of the same size with the bulk connections at GND (for the NMOS) and VDD (for the PMOS), and connecting the gates to the bulk, how will the following parameters change? For each of the parameters place an “X” in the appropriate column of the table. Parameter Increase Decrease Stays the same Cannot be determined Input capacitance X Intrinsic cap X (X) Intrinsic delay X (X) Inverter VM X Drive current X Leakage current X (X) Switching energy (X) X Input cap increases due to added well-to-substrate cap needed to be driven by the input. Intrinsic cap stays the same since the source/drain cap to bulk are not changed. (also accepted cannot be determined) Intrinsic delay decreases since more drive current is available to drive the intrinsic load cap. (also accepted cannot be determined) Inverter VM stays the same since PMOS and NMOS current increase by the same amount. Inverter drive current increases due to the reduction in threshold voltage by forward body bias. Inverter leakage current increases due to smaller effective threshold. (we also accept if you considered only off current and answered stays the same) Switching energy stays the same since the intrinsic load cap is not changed. (also OK if you considered gate cap and answered increase)EECS 141: FALL 2005—FINAL 3PROBLEM 2: Logic (9 pts) a. Find the logical effort of the composite logic block below. (4 pts) Hint: consider path logical effort. IN11.5a2.5a2.5b1.5b32OUTcomposite logic block b. This logic block is placed in a circuit shown above. Write an expression for the propagation delay from input to output (the delay is normalized to tp0). Assume γ = 1. (3 pts) Use stage-based delay calculation approach. Main point to realize is that parasitic cap of the second stage is different for L→H and H→L: For L→H, we compare total output W to 2/1 inverter (2.5b/1.25b inverter for simpler calculation). We get P (L→H) = 4b/3.75b = 16/15. For H→L, we compare total output W to 2/1 inverter (3b/1.5b) and obtain P (H→L) = 4b/4. 5b = 8/9. c. Find a and b for optimum tpLH. (2 pts) Take partial derivative of D(L→H) w.r.t. a and b. a = (8/15)1/3 = 0.81, b = 4a2 = 2.62 Observe that 1.5a > 1 (assuming min transistor size is 1) D (H→L) = (1+4a) + (1 + b/a) + (8/9 + 1/3*32/1.5b) D (L→H) = (1+4a) + (1 + b/a) + (16/15 + 2/3*32/2.5b) LE (H→L) = 0.89 (also accepted 1/3) LE (L→H) = 1.07 (also accepted 2/3) a (L→H) = 0.81 b (L→H) = 2.62 Parameters a and b don’t affect LE. Consider path effort to obtain LE. H→L transition (OUT pull-down): First stage LE = 1*(1+2.5/1.5) = 2.67 Second stage LE = 1/3 Total LE (H→L) = LE1*LE2 = 0.89 L→H transition (OUT pull-up): First stage LE = 1*(1+1.5/2.5) = 1.6 Second stage LE = 2/3 Total LE (L→H) = LE1*LE2 = 1.07 ------------------------------------------------- We also accepted if you did not consider branching at first stage. LE (H→L) = 1/3 LE (L→H) = 2/3EECS 141: FALL 2005—FINAL 4PROBLEM 3: Layout techniques (15 pts) a. Write out the truth table that corresponds to the following stick diagram. (2 pts) VDDOUTABBACGND _______ b. Implement F = AB+AC in one diffusion region using stick diagram. Each gate must be used for both PMOS and NMOS. Use static CMOS. Clearly denote if crossing wires are connected or not. Use the fewest number of transistors possible. (4 pts) VDDFBACGND c. Repeat part (b) for dynamic CMOS using a PUN. All PMOS transistors must share one diffusion. (3 pts) VDDFBACGNDΦ A B C OUT 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 ______ F = A(B+C)EECS 141: FALL 2005—FINAL 5d. Implement the following circuit in stick diagram. Assume all inputs are given and do not break the diffusion. (2 pts) BBBAAOUT BABAOUT e. Fill out the table using only one word per entry. (4 pts) Logic Family Advantage Disadvantage Standard CMOS Robust Area Dynamic Delay Power PTL Area Swing RTL Area PowerEECS 141: FALL 2005—FINAL 6PROBLEM 4: Sequential circuits and their building blocks (11 pts) X and Y are the sizing factors. For the unit sized inverter assume γ = 1, Cin = 2 fF, Req = 5 KΩ. IN1XYCLOUT a. Assume CL = 0 and IN is a perfect 5 GHz clock with 50% duty cycle. Graph OUT and label important points on the x-axis. Do not label more than two points. X = Y = 1. (4 pts) time[ps]Vin0VDDtime[ps]Vout0VDD100 200 300 40027.616.1 tp0 = 0.69RC = 6.9ps Critical path delay (normalized to tp0): (1+4/3) + (2+1) + (0+1) = 6.33 tp1 = 43.7ps Other path delay (normalized to tp0): (2+1) + (0+1) = 4 tp2 = 27.6ps The difference determines pulse width: PW = 2.33tp0 = 16.1psEECS 141: FALL 2005—FINAL 7b. Assume CL = 100 fF. Given IN is a perfect 500 MHz clock signal with 50% duty cycle. Size X and Y such that OUT is a 500 MHz clock signal with 10% duty cycle and minimized propagation delay. (4 pts) Clock is high for 1ns, want 200ps: tp0*(1+4/3*X) = 200ps ⇒ X = 21 For fixed X, delay is minimized when SE of the last two stages is equal: SE2 = Y/X, SE3 = 50/Y. Y = (21*50)1/2 = 32.4 c. What is the functionality of the circuit below? Why is it advantageous to implement its functionality in this manner? (3 pts) DClkClkVDDClkClkVDDQI1 Functionality: flip-flop Why is this circuit good: C2MOS ⇒ no skew Main reason to use inverter I1: buffer (avoid loading of state node) X = 21 Y = 32.4EECS 141: FALL 2005—FINAL 8PROBLEM 5: Timing (10 pts) The notation for each path is (min-Delay, max-Delay). Reg RegClk3Clk2Reg RegClk1Clk1(2,9)(2,4)(1,5)(2,5)(4,8)Logic 2Logic 1(1,6) The above is a register based system. The registers have following characteristics: (min-tCQ, max-tCQ) = (0.5, 2), tsetup = 1, thold = 1. a.
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