EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 21Lecture 21Domino LogicDomino LogicPower RevisitedPower RevisitedEE1412EECS141AnnouncementsAnnouncements Homework 8 due next Thursday Project phase two in lab this week Friday is a holiday Makeup lab on Thursday, 3pm Phase 2 reports due on Monday Phase 3 next weekEE1412EE1413EECS141Midterm 2Midterm 2 Hi: 50 Lo: 21 Avg/Median: 38/39 Project, phase 1, avg: 90.5EE1414EECS141EE1413EE1415EECS141Class MaterialClass Material Last lecture Dynamic logic Today’s lecture Finish domino logic Revisit power Reading Chapter 6, Chapter 7EE1416EECS141Domino LogicDomino LogicEE1414EE1417EECS141Domino LogicDomino LogicIn1In2PDNIn3MeMpClkClkOut1In4PDNIn5MeMpClkClkOut2Mkp1 → 11 → 00 → 00 → 1EE1418EECS141Why Domino?Why Domino?ClkClkIniPDNInjIniInjPDNIniPDNInjIniPDNInjLike falling dominos!EE1415EE1419EECS141Properties of Domino LogicProperties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effortEE14110EECS141EE1416EE14111EECS141EE14112EECS141EE1417EE14113EECS141Designing with Domino LogicDesigning with Domino LogicMpMeVDDPDNClkIn1In2In3Out1ClkMpMeVDDPDNClkIn4ClkOut2MrVDDInputs = 0during prechargeCan be eliminated!EE14114EECS141Footless DominoFootless DominoThe first gate in the chain needs a foot switchPrecharge is rippling – short-circuit currentA solution is to delay the clock for each stageVDDClk MpOut1In11 0VDDClk MpOut2In2VDDClk MpOutnInnIn31 00 1 0 1 0 11 0 1 0EE1418EE14115EECS141Differential (Dual Rail) DominoDifferential (Dual Rail) DominoABMeMpClkClkOut = AB!A !BMkpClkOut = ABMkpMpSolves the problem of non-inverting logic1 0 1 0onoffEE14116EECS141npnp--CMOSCMOSIn1In2PDNIn3MeMpClkClkOut1In4PUNIn5MeMpClkClkOut2(to PDN)1 → 11 → 00 → 00 → 1Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUNEE1419EE14117EECS141NORA LogicNORA LogicIn1In2PDNIn3MeMpClkClkOut1In4PUNIn5MeMpClkClkOut2(to PDN)1 → 11 → 00 → 00 → 1to otherPDN’sto otherPUN’sWARNING: Very sensitive to noise!EE14118EECS141Power Power RevisitedRevisitedEE14110EE14119EECS141Transition Activity and PowerTransition Activity and Power Energy consumed in N cycles, EN:EN= CL• VDD2• n0→1n0→1 – number of 0→1 transitions in N cyclesfVCNnfNEPDDLNNNavg⋅⋅⋅⎟⎠⎞⎜⎝⎛=⋅=→∞→∞→210limlimfNnN⋅=→∞→→1010limαfVCPDDLavg⋅⋅⋅=→210αEE14120EECS141“Dynamic” or timing dependent component ÅType of Logic Function (NOR vs. XOR)“Static” component (does not account for timing)ÅCircuit TopologyÅType of Logic Style (Static vs. Dynamic)ÅSignal StatisticsÅInter-signal Co rrelationsÅSignal Statistics and CorrelationsFactors Affecting Transition ActivityFactors Affecting Transition ActivityEE14111EE14121EECS141Type of Logic Function: NOR vs. XORType of Logic Function: NOR vs. XOR011001010100OutBAExample: Static 2-input NOR GateAssume signal probabilitiespA=1 = 1/2pB=1 = 1/2Then transition probabilityp0→1 = pOut=0 x pOut=1= 3/4 x 1/4 = 3/16α0→1= 3/16If inputs switch every cycleEE14122EECS141EE14112EE14123EECS141Type of Logic Function: NOR vs. XORType of Logic Function: NOR vs. XOR011101110000OutBAExample: Static 2-input XOR GateAssume signal probabilitiespA=1 = 1/2pB=1 = 1/2Then transition probabilityp0→1 = pOut=0 x pOut=1= 1/2 x 1/2 = 1/4α0→1= 1/4If inputs switch in every cycleEE14124EECS141Power Consumption of Dynamic GatesPower Consumption of Dynamic GatesIn1In2PDNIn3MeMpCLKCLKOutCLPower only dissipated when previous Out = 0EE14113EE14125EECS141Dynamic Power Consumption is Dynamic Power Consumption is Data DependentData Dependent011001010100OutBADynamic 2-input NOR GateAssume signal probabilitiesPA=1 = 1/2PB=1 = 1/2Then transition probabilityP0→1 = Pout=0 x Pout=1= 3/4 x 1 = 3/4Switching activity always higher in dynamic gates!P0→1 = Pout=0EE14126EECS141VddIIVddININBOUTBOUT Guaranteed transition for every operation!α0->1 = 1Dynamic CVSLDynamic CVSLEE14114EE14127EECS141ClockClock Always switches Consumes 25-50% of power Clock gating commonly employedEE14128EECS141Problem: Problem: ReconvergentReconvergentFanoutFanoutABXZReconvergenceP(Z = 1) = P(B = 1) . P(X = 1 | B=1)Becomes complex and intractable fastEE14115EE14129EECS141InterInter--Signal CorrelationsSignal CorrelationsLogic withoutreconvergent fanoutLogic with reconvergent fanoutABZCAZCBp0→1=(1 –pApB) pApBP(Z = 1) = p(C=1 | B=1) p(B=1)p0→1= 0 Need to use conditional probabilities to model inter-signal correlations CAD tools required for such analysis EE14130EECS141GlitchingGlitchingin Static CMOSin Static CMOSABXCZABC 101 000XZ Gate DelayAlso known asdynamic hazardsThe result is correct,but there is extra power dissipatedEE14116EE14131EECS141Example: Chain of NOR GatesExample: Chain of NOR Gates1Out1Out2Out3Out4Out50 200 400 6000.01.02.03.0Time (ps)Voltage (V)Out8Out6Out2Out6Out1Out3Out7Out5EE14132EECS141Principles for Power ReductionPrinciples for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question Reducing thresholds to improve performance increases leakage Reduce switching activity Reduce physical capacitanceEE14117EE14133EECS141Next LectureNext Lecture Sequential
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