EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 16Lecture 16SRAMSRAMEE1412EECS141AnnouncementsAnnouncements Hardware lab this week Lab 4, 5 reports due this week Homework #6 due today Homework #7 due next Tuesday Project phase one in lab next weekEE1412EE1413EECS141Class MaterialClass Material Last lecture Design for speed Logical effort Today’s lecture SRAM Register files Reading (Chapters 12, 6)EE1414EECS141Semiconductor Semiconductor MemoryMemoryEE1413EE1415EECS141ArrayArray--Structured Memory ArchitectureStructured Memory ArchitectureEE1416EECS141Semiconductor Memory ClassificationSemiconductor Memory ClassificationRead-Write MemoryNon-VolatileRead-WriteMemoryRead-Only MemoryEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFOEE1414EE1417EECS141ReadRead--Write Memories (RAM)Write Memories (RAM) STATIC (SRAM) DYNAMIC (DRAM)Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferentialPeriodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle EndedEE1418EECS141Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1Vo2Vo2 =Vi1Vo1=Vi2Vo1Vi25Vo1Vi25Vo1Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1EE1415EE1419EECS141MetaMeta--StabilityStabilityGain should be larger than 1 in the transition regionACδBVi2= Vo1Vi1 = Vo2ACδBVi2 = Vo1Vi1 = Vo2EE14110EECS141Writing into a CrossWriting into a Cross--Coupled PairCoupled PairCan implement as a transmission gate as wellAccess transistor must be able to overpower the feedbackEE1416EE14111EECS141EE14112EECS141EE1417EE14113EECS141Memory CellMemory CellComplementary data values are written (read) from two sidesEE14114EECS14166--transistor CMOS SRAM Cell transistor CMOS SRAM Cell WLBLVDDM5M6M4M1M2M3BLQQEE1418EE14115EECS141SRAM OperationSRAM Operation0101WriteHoldEE14116EECS141SRAM OperationSRAM Operation01Reading the cell should not destroy the stored valueReadEE1419EE14117EECS141CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)WLBLVDDM5M6M4M1VDDVDDVDDBLQ=1Q=0CbitCbitEE14118EECS141CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)000.20.40.60.811.20.5Voltage rise [V]11.2 1.5 2Cell Ratio (CR)2.5 3Voltage Rise (V)EE14110EE14119EECS141CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) BL=1 BL=0Q=0Q=1M1M4M5M6VDDVDDWL()()64//LWLWPR =EE14120EECS141CMOS SRAM Analysis (Write)CMOS SRAM Analysis (Write)EE14111EE14121EECS141Read Static Noise MarginRead Static Noise MarginSNMObtained by breaking thefeedback between the invertersEE14122EECS141EE14112EE14123EECS1416T6T--SRAM SRAM ——Layout Layout VDDGNDWLBL BLBCompact cellBitlines: M2Wordline: bootstrapped in M3EE14124EECS14165nm SRAM65nm SRAM ST/Philips/MotorolaAccess TransistorPull downPull upEE14113EE14125EECS141EE14126EECS141Register FileRegister File Schematic very similar to SRAM cell But layout different Sizing different Needs multiple read/write portsEE14114EE14127EECS141Register FileRegister FileBL1WL1BL1BL2BL2WL2Single portTwo-portEE14128EECS141Register fileRegister fileBLWWLWBLRWLREE14115EE14129EECS141Next LectureNext Lecture Combinational logic
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