1EE141 – Fall 2005Lecture 25Power Distribution Power Distribution MemoryMemoryEE141 2Administrative Stuff Project-2 presentations next Tuesday• Sign up for time slot in 353 Cory• Presentation template on web-site Electronic submission (due Monday 11pm)• PPT slides, pre-layout netlist, post-layout netlist• E-mail to: [email protected] Last lecture on Thursday• Memory, overview of future trends in digital IC design• Project 2 + Final discussion• Also HKN review. Your feedback is important!2EE141 3Class Material Today’s lecture• Power distribution• Interconnect effects− Resistive− Inductive• Memory− SRAM− ROMEE141 4ESD Protection When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate – need guard rings to pick it up.3EE141 5ESD ProtectionDiodePADVDDRD 1D 2XCEE141 6Chip Packaging•Bond wires (~25µm) are used to connect the package to the chip• Pads are arranged in a frame around the chip• Pads are relatively large (~100µm in 0.25µm technology),with large pitch (100µm)•Many chips areas are ‘pad limited’ChipMountingCavityLead FrameBonding WirePinLL’4EE141 7Pad FrameLayout Die PhotoPower DistributionPower Distribution5EE141 9Impact of Resistance We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution:• IR drop• Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gatesEE141 10RI Introduced NoiseM1XIRR∆Vfpre∆VVDDVDD-∆VI6EE141 11Source: Cadence••Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction••Heavily influenced by packaging technologyHeavily influenced by packaging technologyBeforeBeforeAfterAfterResistance and the Power Distribution ProblemEE141 12Power Distribution Low-level distribution is in Metal 1 Power has to be “strapped” in higher layers of metal The spacing is set by IR drop, electromigration, inductive effects Always use multiple contacts on straps7EE141 13Power and Ground DistributionGNDVDDLogicGNDVDDLogicGNDVDD(a) Finger-shaped network (b) Network with multiple supply pinsEE141 143rd “coarse and thick” metal layer added to thetechnology for EV4 designPower supplied from two sides of the die via 3rd metal layer2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routingMetal 3Metal 2Metal 1Courtesy Compaq3 Metal Layer Approach (EV4)8EE141 154th “coarse and thick” metal layer added to thetechnology for EV5 designPower supplied from four sides of the dieGrid strapping done all in coarse metal90% of 3rd and 4th metals used for power/clock routingMetal 3Metal 2Metal 1Metal 44 Metal Layers Approach (EV5)Courtesy CompaqEE141 162 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/VssSignificantly lowers resistance of gridLowers on-chip inductanceMetal 4Metal 2Metal 1RP2/VddRP1/VssMetal 3Courtesy Compaq6 Metal Layer Approach (EV6)9EE141 17Limits dc-current to 1 mA/µmElectromigration (1)EE141 18Electromigration (2)10EE141 19The Impact of ResistivityCN-1CNC2R1R2C1TrVinRN-1 RN0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L Diffused signal Diffused signal propagationpropagationDelay ~ LDelay ~ L22The distributed The distributed rcrc--linelineEE141 20The Global Wire ProblemChallenges No further improvements to be expected after the introduction of Copper (superconducting, optical?) Design solutions• Use of fat wires• Insert repeaters — but might become prohibitive (power, area)• Efficient chip floorplanning Towards “communication-based” design • How to deal with latency?• Is synchronicity an absolute necessity?()outwwdoutdwwdCRCRCR693.0CR377.0T+++=11EE141 21# of metal layers is steadily increasing due to:• Increasing die size and device count: we need more wires and longer wires to connect everything• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC substratepolyM1M2M3M4M5M6TinsHWSρ = 2.2 µΩ-cm0.25 µm wiring stackInterconnect: # or Wiring LayersMinimum Widths (Relative)0.00.51.01.52.02.53.03.51.0µ 0.8µ 0.6µ 0.35µ 0.25µM5M4M3M2M1PolyMinimum Spacing (Relative)0.00.51.01.52.02.53.03.54.01.0µ 0.8µ 0.6µ 0.35µ 0.25µM5M4M3M2M1PolyEE141 22 Copper is planned in full sub-0.25 µm process flows and large-scale designs (IBM, Motorola, IEDM97) With cladding and other effects, Cu ~ 2.2 µΩ-cm vs. 3.5 for Al(Cu) ⇒ 40% reduction in resistance Electromigration improvement; 100X longer lifetime (IBM, IEDM97)• Electromigration is a limiting factor beyond 0.18 µm if Al is used (HP, IEDM95)VIASInterconnect Projections: Copper12EE141 23yxdestinationManhattansourcediagonal• 20+% Interconnect length reduction• Clock speedSignal integrityPower integrity• 15+% Smaller chips plus 30+% via reductionCourtesy Cadence X-initiativeDiagonal WiringEE141 24RepeaterReducing RC Delay13EE141 25Taking the repeater loading into accountFor a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The delay of these wire segments is independent of the routing layer!Repeater Insertion (Revisited)INTERCONNECT:Dealing with Dealing with InductanceInductance14EE141 27CLV’DDVDDLi(t)VoutVinGND ’LL di/dt Change in current induces the change in voltage Longer supply lines have larger LImpact of inductance on supply voltageEE141 28tttvoutiLvL20mA40mA5V0.2V0.01.02.03.04.05.0Vout(V)01020IL (mA)246810t (nsec)-0.3-0.10.10.30.5VL(V)tfall = 0.5 nsectfall = 4 nsecSignals Waveforms for Output Driver connected To Bonding Pads(a) vout; (b) iL and (c) vL.The Results of an Actual Simulation are Shown on the Right Side.tf= 4nstf= 0.5nsL di/dt: Simulation15EE141 29Choosing the Right PinChipMountingCavityLead FrameBonding WirePinLL’EE141 30SUPPLYBoardwiringBondingwireDecouplingcapacitorCHIPCd12Decoupling Capacitors On the board (right under the supply pins) On the chip (under the supply straps, near large buffers)Decoupling capacitors are added:16EE141 31Decoupling Capacitor
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