EECS141: SPRING 04—PROJECT 1 1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Prof. Jan Rabaey EECS 141 Spring 2004 Project 1 Due Friday, March 19th, 5pm @ 558 Cory Name (Last, First) Student ID Design Group Scoreboard Phase-1 Phase-2 Phase-3 Total (pts)EECS141: SPRING 04—PROJECT 1 2 Background Information You are given technology parameters that are essential in propagation delay analysis. These parameters are extracted by curve fitting simulated results of an inverter delay in our 0.25µm technology, as shown in Fig. 1. Figure 1: Extraction of delay parameters: (a) tp0, γ, (b) Von, αd. (Wp/Wn=2µ/1µ, L=0.25µ) Parameters tp0 and γ will aid in calculation of the gate delay as given by: 01ppfttγ⎛⎞=⋅+⎜⎟⎝⎠ (1) where tp0 is the intrinsic delay of an inverter, f is the fanout, and γ = Cintrinsic/Cgate is the ratio of the input intrinsic to the input gate capacitance. Parameters Von and αd are intrinsically related, but not equal to the transistor threshold voltage and velocity saturation index. They are simply fitting parameters that provide the most accurate model of a FO4 inverter delay over a range of supply voltages. Fanout of four is chosen for calibration simply because it is the most typical fanout found in well-designed digital circuits. It also represents good average fanout, so we will use the same parameters for all other fanouts that we are going to encounter in this design project. Relationship between the propagation delay of a FO4 inverter and the power supply Vdd is given by: ()dddpddd onVtKVVα=⋅− (2) where Kd is another fitting parameter, but it is not crucial for our problem setup. It lumps some technology parameters including linearized delay capacitance. You will find equation (2) useful in Vdd-based optimizations.EECS141: SPRING 04—PROJECT 1 3 Phase 1: Optimal Design You have to design an 8-input decoder, which implements the following 256 functions: ABCDEFGHFHGFEDCBAFHGFEDCBAF ===25510;;; K You may assume that all 8 inputs (A, B, C, D, E, F, G, H) are available in non-inverted and inverted format. Figure 2: An 8 input decoder. First, find the implementation and sizing that leads to the minimum possible delay. You are free to choose the topology of the gate (types of gates, number of gates in sequence) – Bear in mind however the following constraints: • The load on the input signal (that is, the input capacitance of your network) should not be larger than that of a minimum size inverter. • Every output is loaded with a capacitance equal to 128 times the input capacitance of a minimum size inverter. • Only static complementary CMOS gates can be used. • Identical gates (that is, gates of the same type with the same inputs) can appear only ONE TIME. This means that gates should be shared between different paths if possible. What is the value of Dmin normalized to tp0 (it should be the same for all 256 outputs). What is the energy Eref that corresponds to the minimum delay? Since the energy depends upon how many inputs are changing, consider only the case where one input changes state (from 0 to 1 or vice versa). Assume VDD = VDDnom = 2.5V. Express Eref in terms of energy required to drive the input gate capacitance Cgate = 1 (call this number “1”, it is simply a reference case, you do not need value in fF in your calculations) of the first gate in the chain. Now, you obtained reference point (Dmin, Eref) for your optimizations.EECS141: SPRING 04—PROJECT 1 4 Phase 2 – Reducing the Energy Assume now that you are allowed to increase the delay by {10,20,30}%. For the newly specified delay, perform the following three optimizations in order to minimize the total energy of the reference design. a) Gate size (W)/topology optimization What is the new topology and the device sizes that minimizes the energy? What is the achieved percent energy reduction, ERW = 100(1 – EW/Eref)? b) Supply voltage (Vdd) optimization What is the value of the new supply voltage, VDDopt? What is the achieved percent energy reduction, ERVdd = 100(1 – EVdd/Eref)? Clearly show your design methodology and summarize all results in following Table: Summary of results from Phase-1: Dmin (tp0) = Eref = Opt. case ER (%) VDDopt Reference 0% 2.5V W 2.5V Vdd Phase 3: Verification in HSPICE Using HSPICE, verify results of your optimizations from Phase I and II. a) Obtain reference point (Dmin, Eref) in HSPICE. Is it different from what you expected? (Hint: To determine energy dissipated in driving the input gate capacitance in HSPICE verification, you may want to use some of the results from background section and/or use HSPICE to estimate this energy) b) Using parameters (gate size, VDDopt) from Phase II, report achieved delay increase DI and achieved energy reduction ER for both optimization cases. Normalize numbers relative to the reference case (Dmin, Eref) obtained by HSPICE in part (a) of Phase-2. Comment on your results. Summary of results from Phase-3: Dmin (ps) Eref (Ein-1st stage) HSPICE Phase-1 HSPICE Phase-1 Reference ER (%) DI (%) Verification HSPICE Phase-2 HSPICE Phase-2
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