EE1411EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsCircuitsCircuitsLecture 10Lecture 10EE141EECS1411Lecture #10Buffer SizingBuffer SizingTechnology ScalingTechnology ScalingAnnouncementsAnnouncements No Lab this week Lab 5 next week (last software lab) Homework #4 due Mo March 3 No new homework this week Midterm 1 next Friday!EE141EECS1412Lecture #10 Review session on Th 2/28 5pm in 203 McLaughlin Covers lectures 1-8 (not including power)EE1412Class MaterialClass Material Last lecture Power dissipation Buffer sizing (intro) Today’s lecture Buffer sizing (cntd), technology scalingEE141EECS1413Lecture #10 Reading (5.5, 5.6)Sizing of an Sizing of an Inverter ChainInverter ChainEE141EECS1414Lecture #104EE1413Inverter ChainInverter ChainInOutCL For some given CL:How many stages are needed to minimize delay?EE141EECS1415Lecture #10How many stages are needed to minimize delay? How to size the inverters? Anyone want to guess the solution?DelayCP= 2WCg2WReview: Inverter with LoadReview: Inverter with LoadLoadCintCLCN= WCgWEE141EECS1416Lecture #10EE1414()~Wint LDelay R C C+Delay FormulaDelay Formula()()in int/pW inLininvtkRCCCCC t fγ=+=+Cint= γCin(γ≈1 for inverter)f = CL/Cin– electrical fanoutR=R(L/W);C=3WCCintCLCinEE141EECS1417Lecture #10RW Rsq(L/W);Cin3WCgtinv= 3·ln(2)·L·RsqCgtinvis independent of sizing of the gate!!!inIn OutApply to Inverter ChainApply to Inverter ChainCL12 Ntp= tp1+ tp2+ …+ tpN,1in jpj invijCttCγ+⎛⎞=+⎜⎟⎜⎟⎝⎠EE141EECS1418Lecture #10,injC⎝⎠,1,,111,, NNin jppjinv inNLjiin jCttt CCCγ++==⎛⎞== + =⎜⎟⎜⎟⎝⎠∑∑EE1415Optimal Tapering for Given Optimal Tapering for Given NN Delay equation has N-1 unknowns, Cin,2… Cin,N,110pinjdt Ctt+=−= To minimize the delay, find N-1 partial derivatives:,,1,1 ,... ...in j in jpinv invin j in jCCtt tCC+−=+ + +EE141EECS1419Lecture #102,,1,0inv invin j in j in jttdC C C−Optimal Tapering for Given Optimal Tapering for Given NN(cont’d)(cont’d) Result: every stage has equal fanout: In other words, size of each stage is geometric mean of two neighbors:,,1,1 ,in j in jin j in jCCCC+−=EE141EECS14110Lecture #10,,1,1in j in j in jCCC−+= Equal fanout Æ every stage will have same delayEE1416Optimum Delay and Number of StagesOptimum Delay and Number of Stages When each stage has same fanout f :,1/NLinfFCC==NFf = Effective fanout of each stage:EE141EECS14111Lecture #10()NpinvtNt Fγ=+ Minimum path delay:ExampleExampleInOutCL= 8 C1C11 ff 2CL/C1has to be evenly distributed across N = 3 stages:EE141EECS14112Lecture #10283==fEE1417Delay Optimization Problem #2Delay Optimization Problem #2 You are given: The size of the first inverter The size of the load that needs to be driven Your goal: Minimize delay by finding optimal number and sizes of gatesSo, need to find N that minimizes:EE141EECS14113Lecture #10So, need to find N that minimizes:()Npinv LintNt CCγ=+()lnLinNCCfCC NSolving the OptimizationSolving the Optimization Rewrite N in terms of fanout/stage f:()()()1/lnlnNp inv L in inv L inftNtCC t CCfγγ⎛⎞+=+=⎜⎟⎝⎠ln 1tffγ∂−−()lnLinNLinfCC Nf=→=EE141EECS14114Lecture #10()2ln 1ln 0lnpinv L intfftCCffγ∂=⋅=∂Forγ= 0, f = e, N = ln (CL/Cin)()ffγ+= 1expEE1418Optimum Effective Fanout Optimum Effective Fanout ff()ffγ+= 1exp Optimum f for given process defined by γ3.544.55foptf=36EE141EECS14115Lecture #100 0.5 1 1.5 2 2.5 32.53γfopt= 3.6for γ = 1eIn Practice: Plot of Total DelayIn Practice: Plot of Total Delay[Hodges, p.281]EE141EECS14116Lecture #1016 Curves very flat for f > 2 Simplest/most common choice: f = 4EE1419()Normalized Delay Function of Normalized Delay Function of FF(),Npinv LintNt FFCCγ=+ =EE141EECS14117Lecture #10Textbook: page 210(γ = 1)Buffer DesignBuffer Design1Nf tp16465111864641646528183415EE141EECS14118Lecture #1011646442.881622.634154 2.8 15.3EE14110What About Power Consumption What About Power Consumption (and Area)?(and Area)?Ignoring diffusion capacitance:Ctot= Cin+ f·Cin+ … + fN·Cin= Cin·(1 + f + … + fN)= Cin+ Cin·fN+ Cin·f·(1 + f + … + fN-2)EE141EECS14119Lecture #10Overhead !!! f(fN-1-1) / (f-1)Example (γ=0): CL= 20pF; Ci= 50fF → N = 6Fixed: 20pFOverhead: 11.66pF !!!Example Overhead NumbersExample Overhead NumbersExample: CL= 20pF; Cin= 50fF2525401015202510152025head Capacitance (pF)25303540Delay (tinv)EE141EECS14120Lecture #102 3 4 5 6 7 8 9 10052 3 4 5 6 7 8 9 1005Overh2 3 4 5 6 7 8 9 101520Number of StagesEE14111Impact ofImpact ofTechnology ScalingTechnology ScalingEE141EECS14121Lecture #10Goals of Technology ScalingGoals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Or build same products cheaper Price of a transistor has to be reducedBut also want to be faster smallerEE141EECS14122Lecture #10But also want to be faster, smaller, lower powerEE14112Technology ScalingTechnology Scaling Benefits of 30% “Dennard” scaling (1974): Double transistor density Reduce gate delay by 30% (increase operating frequency by 43%) Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency)Die size used to increase by 14% perEE141EECS14123Lecture #10Die size used to increase by 14% per generation (not any more) Technology generation spans 2-3 yearsMoore was not always accurateMoore was not always accurateEE141EECS14124Lecture #10EE14113Technology Scaling (1)Technology Scaling (1)1022X reduction every 5 years-1100101mum Feature Size (micron)2X reduction every ~5 yearsEE141EECS14125Lecture #10Minimum Feature SizeMinimum Feature Size1960 1970 1980 1990 2000 201010-2101YearMinimTechnology Scaling (2) Technology Scaling (2) EE141EECS14126Lecture #10Number of components per chipNumber of components per chipEE14114Technology Scaling (3)Technology Scaling (3)tpdecreases by 30%/yearf increases by 43%EE141EECS14127Lecture #10Propagation DelayPropagation DelayTechnology Scaling (4)Technology Scaling (4)100x1.4 / 3 years1000∝ κ 0.70.1110100Power Dissipation (W)x4 / 3 yearsMPU101001000∝ κ 3ower Density (mW/mm2)∝EE141EECS14128Lecture #10(a) Power dissipation vs. year.959085800.01YearMPU DSPScaling Factor κ （normalized by 4μm design rule）1011Po(b) Power density vs. scaling factor.From KurodaEE14115Technology Scaling Models Technology Scaling Models •
View Full Document
Unlocking...