1EE1411EE141 – S04Performance (cntd)PowerEE141EE141--Spring 2004Spring 2004Lecture 8Lecture 8EE1412EE141 – S04Today’s lectureToday’s lecture Power consumption (wrap-up) Inverter chain sizingEE1413EE141 – S04AnnouncementsAnnouncements Homework 3 due today. Homework 4 will be posted later today. EE1414EE141 – S04Power DissipationPower Dissipation2EE1415EE141 – S04Where Does Power Go in CMOS?Where Does Power Go in CMOS?• Dynamic Power Consumption• Short Circuit Currents• LeakageCharging and Discharging CapacitorsShort Circuit Path between Supply Rails during SwitchingLeaking diodes and transistorsEE1416EE141 – S04Transistor LeakageTransistor Leakage Transistors that are supposed to be off -leakInput at VDDInput at 0VDD0VVDDILeakVDD0VVDDILeakEE1417EE141 – S04The SubThe Sub--Micron MOS TransistorMicron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic ResistancesEE1418EE141 – S04Threshold VariationsThreshold VariationsVTLLong-channel thresholdLow VDSthresholdThreshold as a function of the length (for low VDS) Drain-induced barrier lowering (for low L)VDSVT3EE1419EE141 – S04SubSub--Threshold ConductionThreshold Conduction0 0.5 1 1.5 2 2.510-1210-1010-810-610-410-2VGS(V)ID(A)VTLinearExponentialQuadraticTypical values for S:60 .. 100 mV/decadeThe Slope FactoroxDnkTqVDCCneIIGS+= 1 ,~0S is ∆VGSfor ID2/ID1=10GSDSubCiCdEE14110EE141 – S04Inverter DelayInverter Delay• Minimum length devices, L=0.25µm• Assume that for WP= 2WN =2W • same pull-up and pull-down currents• approx. equal resistances RN= RP• approx. equal rise tpLHand fall tpHLdelays• Analyze as an RC networkWNunitNunitunitPunitPRRWWRWWRR ==⎟⎟⎠⎞⎜⎜⎝⎛≈⎟⎟⎠⎞⎜⎜⎝⎛=−− 11tpHL= (ln 2) RNCLtpLH= (ln 2) RPCLDelay (D):2WWunitunitginCWWC 3=Load for the next stage:EE14111EE141 – S04SubSub--Threshold Threshold IIDDvsvsVVGSGSVDSfrom 0 to 0.5V⎟⎟⎠⎞⎜⎜⎝⎛−=−kTqVnkTqVDDSGSeeII 10EE14112EE141 – S04SubSub--Threshold Threshold IIDDvsvsVVDSDS()DSkTqVnkTqVDVeeIIDSGS⋅+⎟⎟⎠⎞⎜⎜⎝⎛−=−λ110VGSfrom 0 to 0.3V4EE14113EE141 – S04Sizing of an Sizing of an Inverter ChainInverter ChainEE14114EE141 – S04Subthreshold Leakage ComponentEE14115EE141 – S04Static Power ConsumptionVin=5VVoutCLVddIstatPstat = P(In=1).Vdd . IstatWasted energy …Should be avoided in most cases,but could help reducing energy in others (e.g. sense amps)EE14116EE141 – S04Principles for Power ReductionPrinciples for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 … 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance5EE14117EE141 – S04Inverter ChainInverter ChainCLIf CLis given:- How many stages are needed to minimize the delay?- How to size the inverters?May need some additional constraints.InOutEE14118EE141 – S04Inverter with LoadInverter with LoadLoad (CL)DelayAssumptions: no load -> zero delayCLtp= kRWCLRWRWWunit= 1k is a constant, equal to 0.69EE14119EE141 – S04Inverter with LoadInverter with LoadLoadDelayCintCLDelay = kRW(Cint+ CL) = kRWCint+ kRWCL= kRWCint(1+ CL/Cint)= Delay (Internal) + Delay (Load)CN= CunitCP= 2Cunit2WWEE14120EE141 – S04Delay FormulaDelay Formula()()()γ/1/1~0intftCCCkRtCCRDelaypintLWpLintW+=+=+Cint= γCginwithγ≈1f = CL/Cgin- effective fanoutR = Runit/W ; Cint=WCunittp0= 0.69RunitCunit6EE14121EE141 – S04Apply to Inverter ChainApply to Inverter ChainCLIn Out12 Ntp= tp1+ tp2+ …+ tpN⎟⎟⎠⎞⎜⎜⎝⎛++jginjginunitunitpjCCCRt,1,1~γLNginNijginjginpNjjppCC CCttt =⎟⎟⎠⎞⎜⎜⎝⎛+==+=+=∑∑1,1,1,01,,1γEE14122EE141 – S04Optimal Tapering for Given Optimal Tapering for Given NNDelay equation has N - 1 unknowns, Cgin,2– Cgin,NMinimize the delay, find N - 1 partial derivativesResult: Cgin,j+1/Cgin,j= Cgin,j/Cgin,j-1Size of each stage is the geometric mean of two neighbors- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay1,1,, +−=jginjginjginCCCEE14123EE141 – S04Optimum Delay and Number of Optimum Delay and Number of StagesStages1,/ginLNCCFf ==When each stage is sized by f and has same eff. fanout f:NFf =()γ/10NppFNtt +=Minimum path delayEffective fanout of each stage:EE14124EE141 – S04ExampleExampleCL= 8 C1InOutC11 ff2283==fCL/C1has to be evenly distributed across N = 3 stages:7EE14125EE141 – S04Optimum Number of StagesOptimum Number of StagesFor a given load, CLand given input capacitance CinFind optimal sizing f()⎟⎟⎠⎞⎜⎜⎝⎛+=+=fffFtFNttpNpplnlnln1/0/10γγγ0ln1lnln20=−−⋅=∂∂fffFtftppγγFor γ= 0, f = e, N = lnFfFNCfCFCinNinLlnln with ==⋅=()ffγ+= 1expEE14126EE141 – S04Optimum Effective Optimum Effective FanoutFanoutffOptimum f for given process defined by γ()ffγ+= 1expfopt= 3.6for γ=10 0.5 1 1.5 2 2.5 32.533.544.55γfoptEE14127EE141 – S04Impact of Loading on Impact of Loading on tptpWith Self-Loading γ=11 1.5 2 2.5 3 3.5 4 4.5 501234567fnormalized delayEE14128EE141 – S04Normalized delay function of Normalized delay function of FF()γ/10NppFNtt +=8EE14129EE141 – S04Buffer DesignBuffer Design111186464646442.881622.6Nf tp16465281834154 2.8 15.3EE14130EE141 – S04What about power consumption (and What about power consumption (and area)?area)?EE14131EE141 – S04Delay versus Area and PowerDelay versus Area and PowerEE14132EE141 – S04Next LectureNext Lecture Technology Scaling Process Variations Introduction to Complex
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