EE24111EE141EE141 - Fall 2000Introduction to DigitalIntegrated CircuitsTu-Th 9:30 - 11:00 am203 McLaughlin2EE141What is this class about?Introduction to digital integrated circuits.CMOS devices and manufacturing technology. CMOS invertersand gates. Propagation delay, noise margins, and powerdissipation. Sequential circuits. Arithmetic, interconnect, andmemories. Programmable logic arrays. Design methodologies.What will you learn?Understanding, designing, and optimizing digital circuits withrespect to different quality metrics: cost, speed, powerdissipation, and reliabilityEE24123EE141Practical InformationInstructors:» Jan Rabaey231 Cory Hall , 666-3111, [email protected] hours: Mo 1:30-3pm (231 Cory); Tu 11-12:00pm (231 Cory)TAs:» Mike Sheets, [email protected]» Radu Zlatanovici, [email protected]» Nathan Chan, [email protected]» Dietrich Ho, [email protected] Hours: 353 Cory“The Paperless Class”http:”//bwrc.eecs.berkeley.edu/classes/ee141”4EE141Discussions & LabsDiscussion Sessions - flexible assignmentMike Sheets & Radu Zlatanovici» M 4-5pm; 299 Cory;» W 4-5pm 285 Cory;Labs - 353 CoryNathan Chan & Dietrich Ho» Mo 8-11am (TBA),» Tu 3-6 pm (TBA),» We 11-2 pm (TBA),» Th 3-6 pm (TBA),» Fr 11-2pm (TBA)EE24135EE141Class Organization+/- 10 assignmentsOne Integrated Design Project with 3deliverablesLaboratories:» 6 software labs» 1 hardware lab2midterms;1final» midterm1: Th 10/5; midterm2: Th 11/2 – both at 6:30pm» final: Fr 15/10 (8-11am)6EE141Grading PolicyHomeworks: 10%Labs: 10%Projects: 20%Midterms: 30%Final: 30%EE24147EE141Class MaterialTextbook: “Digital Integrated Circuits - ADesign Perspective”, by J. RabaeyClass notes: Web page (New stuff!)Lab Reader:Available on the web page!Selected material will be made availablefrom Copy CentralCheck web page for the availability of tools8EE141SoftwareMicromagic “max” and “sue”» A modern version of the good ol’ magic» On-line documentation and tutorialsHSPICE and IRSIM for simulationEE24159EE141Getting StartedAssignment 1: Getting SPICE to work -see web-pageNO discussion sessions or labs thisweek.First discussion sessions in Week 2First Software Lab in Week 210EE141Digital Integrated CircuitsIntroduction: Issues in digital designThe inverter - CMOSCombinational logic structuresSequential logic gates; timingArithmetic building blocksInterconnect: R, L and CMemories and array structuresDesign methodsEE241611EE141Introduction12EE141The First ComputerThe BabbageDifference Engine(1832)25,000 partscost:£17,470EE241713EE141ENIAC - The first electronic computer(1946)14EE141The Transistor RevolutionFirst transistorBell Labs, 1948EE241815EE141The First Integrated CircuitsBipolar logic1960’sECL 3-input GateMotorola 196616EE141Evolution in Transistor CountEE241917EE141Transistor Count in Processors18EE141Transistor size trendsTransistors scale by ~ 30% per generationSource: IntelPentium II(R)Pentium (R)Pentium (R)Pentium MMX(TM)Pentium II (R)Pentium Pro(R)Pentium MMX(TM)Pentium MMX(TM)Pentium(R)PentiumMMX(TM)Pentium (R)Pentium II (R)Pentium Pro(R)Pentium II (R)110100345678Process Technology GenerationTransistor Size (meters)Total TransistorAverage TransistorEE2411019EE141Logic densityShrinks and compactions meet density goalsNew micro-architectures drop densitySource: IntelPentium (R)Pentium Pro (R)486386i86011010010001.5µ1.5µ1.5µ1.5µ1.0µ1.0µ1.0µ1.0µ0.8µ0.8µ0.8µ0.8µ0.6µ0.6µ0.6µ0.6µ0.35µ0.35µ0.35µ0.35µ0.25µ0.25µ0.25µ0.25µ0.18µ0.18µ0.18µ0.18µ0.13µ0.13µ0.13µ0.13µLogic Density2x trendLogic Transistors/mm2Pentium II (R)20EE141Evolution in ComplexityNumber of bits per chip1970 1980 1990 2000 2010Year1Gbits0.15-0.2µm256 Mbits0.25-0.3µm4Gbits0.15µm64 Mbits0.35-0.4µm16 Mbits0.5-0.6µm1Mbits1.0-1.2µm4Mbits0.7-0.8µm256 Kbits1.6-2.4µm64 Kbits101010910810710610510464 Gbits0.08µm*Encyclopedia2 hrs CD Audio30 sec HDTVHuman memoryHuman DNABookPageEE2411121EE141Evolution in Speed/Performance22EE141Processor Frequency TrendEE2411223EE141EvolutioninPerformanceMicroprocessorPower(MIPS)1000.0100.010.01.01980 1985 1990 1995 2000YearP7P6Pentium486386286Actual processingspeed is increasingeven faster24EE141Power Dissipation010203040506070Watts/cm2Surpassed Hot-Plate PowerDensity in 0.6 µµµµmCMOSCourtesy: IntelPentium(R)486386PentiumPro (R)01101001,00010,0001985 1990 1995 2000 2005 2010Icc (amps)100-2,000ampsDue to 30%Vdd scalingEE2411325EE141A Historical Perspective (DEC/Compaq)EV4• 200MHz @100°C & 3.3V• 16 gate delays per cycle• 30W @200MHz & 3.3V• 13.9mm x 16.8mm (233 mm2)• 1.7 Million Transistors~ 0.85 Million Logic TransistorsEV5• 350MHz @100°C & 3.3V• 14 gate delays per cycle• 60W @350MHz & 3.3V• 16.5mm x 18.1mm (298 mm2)• 9.3 Million Transistors~ 2.5 Million Logic TransistorsEV6• 575MHz @100°C & 2.2V• 12 gate delays per cycle• 90W @575MHz & 2.2V• 16.7mm x 18.8mm (314 mm2)• 15.2 Million Transistors~ 6 Million Logic TransistorsEV7• Clock frequency >1.0GHz @ 1.5V• 100W• ~350mm2• ~100 Million transistorsEV8• Clock frequency range 1.0-2.0GHz (0.125micron)• <150W• ~250 Million transistorsSlides Courtesy of Bill Herrick (Compaq)26EE141Challenges in Digital Design“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.Everything Looks a Little Different“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability•etc.…and There’s a Lot of Them!∝∝∝∝ DSM ∝∝∝∝ 1/DSM?EE2411427EE141Intel 4004 Micro-Processor28EE141Intel Pentium (II) microprocessorEE2411529EE141Silicon in 2010Die Area: 2.5x2.5 cmVoltage: 0.6 VTechnology: 0.07 µµµµmDensity Access Time(Gbits/ cm2) (ns)DRAM 8.5 10DRAM (Logic) 2.5 10SRAM (Cache) 0.3 1.5Density Max.Ave.Power ClockRate(Mgates/cm2) (W/cm2) (GHz)Custom 25 54 3Std. Cell 10 27 1.5Gate Array 5 18 1Single-Mask GA 2.5 12.5 0.7FPGA 0.4 4.5 0.2530EE141The ChallengeSource: sematech97A growing gap between design complexity and design productivityEE2411631EE141Design Abstraction
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