EE141EE141EECS1411Lecture #19EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsLectureLecture1919Sequential LogicSequential LogicEE141EECS1412Lecture #19AnnouncementsAnnouncements Homework 8 due today Project phase two posted early next week Midterm 2 next We – 7pm-8:30pm 105 North Gate Review session – Tu evening 6pm (203 McLaughlin)EE141EE141EECS1413Lecture #19Class MaterialClass Material Last lecture Domino logic Today’s lecture Revisit power Sequential logic Reading Chapters 6,7EE141EECS1414Lecture #19Power Power RevisitedRevisitedEE141EE141EECS1415Lecture #19Transition Activity and PowerTransition Activity and Power Energy consumed in N cycles, EN:EN= CL• VDD2• n0→1n0→1 – number of 0→1 transitions in N cyclesfVCNnfNEPDDLNNNavg⋅⋅⋅⎟⎠⎞⎜⎝⎛=⋅=→∞→∞→210limlimfNnN⋅=→∞→→1010limαfVCPDDLavg⋅⋅⋅=→210αEE141EECS1416Lecture #19“Dynamic” or timing dependent component ÅType of Logic Function (NOR vs. XOR)“Static” component (does not account for timing)ÅCircuit TopologyÅType of Logic Style (Static vs. Dynamic)ÅSignal StatisticsÅInter-signal CorrelationsÅSignal Statistics and CorrelationsFactors Affecting Transition ActivityFactors Affecting Transition ActivityEE141EE141EECS1417Lecture #19Type of Logic Function: NORType of Logic Function: NORABOut00 101 010 011 0Example: Static 2-input NOR GateAssume signal probabilitiespA=1 = 1/2pB=1 = 1/2Then transition probabilityp0→1 = pOut=0 x pOut=1= 3/4 x 1/4 = 3/16α0→1= 3/16If inputs switch every cycleEE141EECS1418Lecture #19Type of Logic Function: NANDType of Logic Function: NANDABOut00 101 110 111 0Example: Static 2-input NAND GateAssume signal probabilitiespA=1 = 1/2pB=1 = 1/2Then transition probabilityp0→1 = pOut=0 x pOut=1= α0→1= If inputs switch every cycleEE141EE141EECS1419Lecture #19Type of Logic Function: XORType of Logic Function: XORABOut00 001 110 111 0Example: Static 2-input XOR GateAssume signal probabilitiespA=1 = 1/2pB=1 = 1/2Then transition probabilityp0→1 = pOut=0 x pOut=1= 1/2 x 1/2 = 1/4α0→1= 1/4If inputs switch in every cycleEE141EECS14110Lecture #19Power Consumption of Dynamic GatesPower Consumption of Dynamic GatesIn1In2PDNIn3MeMpCLKCLKOutCLPower only dissipated when previous Out = 0EE141EE141EECS14111Lecture #19Dynamic Power Consumption is Dynamic Power Consumption is Data DependentData DependentABOut00 101 010 011 0Dynamic 2-input NOR GateAssume signal probabilitiesPA=1 = 1/2PB=1 = 1/2Then transition probabilityP0→1 = Pout=0 x Pout=1= 3/4 x 1 = 3/4Switching activity always higher in dynamic gates!P0→1 = Pout=0EE141EECS14112Lecture #19VddIIVddININBOUTBOUT Guaranteed transition for every operation!α0->1 = 1DualDual--Rail DominoRail DominoEE141EE141EECS14113Lecture #19ClockClock Always switches Often consumes 25-50% of total power Clock gating commonly employedEE141EECS14114Lecture #19Problem: Reconvergent FanoutABXZReconvergenceP(Z = 1) = P(B = 1) . P(X = 1 | B=1)Becomes complex and intractable fastEE141EE141EECS14115Lecture #19Inter-Signal CorrelationsLogic withoutreconvergent fanoutLogic with reconvergent fanoutABZCAZCBp0→1=(1 –pApB) pApBP(Z = 1) = p(C=1 | B=1) p(B=1)p0→1= 0 Need to use conditional probabilities to model inter-signal correlations CAD tools best for performing such analysis EE141EECS14116Lecture #19Glitching in Static CMOSGlitching in Static CMOSABXCZABC 101 000XZ Gate DelayAlso known asdynamic hazardsThe result is correct,but there is extra power dissipatedEE141EE141EECS14117Lecture #19Example: Chain of NAND GatesExample: Chain of NAND Gates1Out1Out2Out3Out4Out50 200 400 6000.01.02.03.0Time (ps)Voltage (V)Out8Out6Out2Out6Out1Out3Out7Out5EE141EECS14118Lecture #19Principles for Power ReductionPrinciples for Power Reduction Most important idea: reduce waste Examples: Don’t switch capacitors you don’t need to– Clock gating, glitch elimination, logic re-structuring Don’t run circuits faster than needed– Power α VDD2– can save a lot by reducing supply for circuits that don’t need to be as fast– Parallelism falls into this category Let’s say we do a good job of that – then what?EE141EE141EECS14119Lecture #19Energy Energy ––Performance SpacePerformance Space Plot all possible designs on a 2-D plane No matter what you do, can never get below/to the right of the solid line This line is called “Pareto Optimal Curve” Usually (always) follows law of diminishing returnsPerformanceEnergy/opEE141EECS14120Lecture #19Optimization PerspectiveOptimization Perspective Instead of metrics like EDP, this curve often provides information more directly Ex1: What is minimum energy for XX performance? Ex2: Over what range of performance is a new technique (dotted line) actually beneficial?PerformanceEnergy/opEE141EE141EECS14121Lecture #19Sequential Sequential LogicLogicEE141EECS14122Lecture #19Combinational vs. Sequential LogicCombinational vs. Sequential LogicCombinational SequentialOutput = f(In)Output = f(In, Previous In)CombinationalLogicCircuitOutInCombinationalLogicCircuitOutInStateEE141EE141EECS14123Lecture #19Why Sequencing?Why Sequencing? Two key (related) reasons that we need sequencing: (1) Want to know when an input has a “new”valueEE141EECS14124Lecture #19Why Sequential Logic?Why Sequential Logic? Two key (related) reasons that we need sequencing: (2) Need to slow down signals that are too fast In order to keep them aligned with slower onesEE141EE141EECS14125Lecture #19Latch versus Latch versus Register (FlipRegister (Flip--flop)flop)DClkQDClkQ Register: edge-triggeredstores data when clock rises Clk ClkDDQQ Latch: level-sensitiveclock is low - hold modeclock is high - transparentEE141EECS14126Lecture #19LatchesLatchesInclkInOutPositive LatchCLKDGQOutOutstableOutfollows InInclkInOutNegative LatchCLKDGQOutOutstableOutfollows InEE141EE141EECS14127Lecture #19Characterizing TimingCharacterizing TimingRegisterLatchClkDQtC→QClkDQtC→QtD→QEE141EECS14128Lecture #19Timing DefinitionsTiming DefinitionstCLKtDtc→qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQEE141EE141EECS14129Lecture #19Vi1Vo2Vo2 =Vi1Vo1=Vi2ACBPositive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1Vo1Vo1= Vi2 Vo2Vo1= Vi2 Vo2= Vi1 EE141EECS14130Lecture #19Gain should be larger than 1 in the transition
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