EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 24Lecture 24TimingTimingClock DistributionClock DistributionEE1412EECS141AnnouncementsAnnouncements Homework 8 due today Project phase three in lab this week Project reports due on Monday Poster presentations next weekEE1412EE1413EECS141Class MaterialClass Material Last lecture Multivibrators Timing Today’s lecture Finish timing Clock distribution Reading Chapter 10EE1414EECS141TimingTimingEE1413EE1415EECS141Positive and Negative SkewPositive and Negative SkewR1In(a) Positive skewCombinationalLogicDQtCLK1CLKdelaytCLK2R2DQCombinationalLogictCLK3R3•••DQdelayR1In(b) Negative skewCombinationalLogicDQtCLK1delaytCLK2R2DQCombinationalLogictCLK3R3•••DQdelay CLKEE1416EECS141Positive SkewPositive SkewCLK1CLK2TCLKδTCLK+δ+ thδ2143Launching edge arrives before the receiving edgeEE1414EE1417EECS141Negative SkewNegative SkewReceiving edge arrives before the launching edgeCLK1CLK2TCLKδTCLK-δ2143EE1418EECS141Timing ConstraintsTiming ConstraintsR1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc − qtc − q, cdtsu, tholdtlogictlogic, cdMinimum cycle time:T -δ= tc-q+ tsu+ tlogicWorst case is when receiving edge arrives early (positive δ)EE1415EE1419EECS141Timing ConstraintsTiming ConstraintsR1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc − qtc − q, cdtsu, tholdtlogictlogic, cdHold time constraint:t(c-q, cd)+ t(logic, cd)> thold+ δWorst case is when receiving edge arrives lateRace between data and clockEE14110EECS141Longest Logic Path in Longest Logic Path in EdgeEdge--Triggered SystemsTriggered SystemsClkTTSUTClk-QTlogicLatest point of launchingEarliest arrivalof next cycleTJS + δEE1416EE14111EECS141Clock Constraints in Clock Constraints in EdgeEdge--Triggered SystemsTriggered SystemsIf launching edge is late and receiving edge is early, the data will not be too late if:Minimum cycle time is determined by the maximum delays through the logicTc-q+ Tlogic+ TSU< T – TJS,1–TJS,2-δTc-q+ Tlogic+ TSU+ δ+ 2 TJS< TSkew can be either positive or negativeEE14112EECS141Shortest PathShortest PathClkTclk-q,cdTlogic, cdEarliest point of launchingData must not arrivebefore this timeClkTHNominalclock edgeEE1417EE14113EECS141Clock Constraints Clock Constraints in Edgein Edge--Triggered SystemsTriggered SystemsMinimum logic delay If launching edge is early and receiving edge is late:Tc-q, cd+ Tlogic, cd–TJS,1< TH+ TJS,2+ δTc-q, cd+ Tlogic, cd< TH+ 2TJS+ δEE14114EECS141How to counter Clock Skew?How to counter Clock Skew?REGφREGφREGφ.REGφlogOutInClock DistributionPositive SkewNegative SkewData and Clock RoutingEE1418EE14115EECS141Register Register ––Based TimingBased TimingFlip-flopLogicφ = 1φ = 0Flip-flopdelaySkewLogic delayTSUTClk-QRepresentation after M. Horowitz, VLSI Circuits 1996.EE14116EECS141Registers and Dynamic LogicRegisters and Dynamic Logicφ = 1φ = 0Logic delayTSUTClk-Qφ = 1φ = 0Logic delayTSUTClk-QPrechargeEvaluateEvaluatePrechargeFlip-flops are used only with static logicEE1419EE14117EECS141PipeliningPipeliningREGREGREGlogaCLKCLKCLKOutbREGREGREGlogaCLKCLKCLKREGCLKREGCLKOutbReferencePipelinedEE14118EECS141LatchLatch--Based PipelineBased PipelineF GCLKCLKIn OutC1C2CLKC3CLKCLKCompute F compute GEE14110EE14119EECS141Clock Clock DistributionDistributionEE14120EECS141Clock DistributionClock DistributionCLKClock is distributed in a tree-like fashionH-treeEE14111EE14121EECS141More realistic HMore realistic H--treetree[Restle98]EE14122EECS141The Grid SystemThe Grid SystemDriverDriverDr ive rDr ive rGCLKGCLKGC LKGC LK•No rc-matching•Large powerEE14112EE14123EECS141Example: DEC Alpha 21164Example: DEC Alpha 21164Clock Frequency: 300 MHz - 9.3 Million TransistorsTotal Clock Load: 3.75 nFPower in Clock Distribution network : 20 W (out of 50)Uses Two Level Clock Distribution:• Single 6-stage driver at center of chip• Secondary buffers drive left and right sideclock grid in Metal3 and Metal4Total driver size: 58 cm!EE14124EECS14121164 Clocking21164 Clocking 2 phase single wire clock, distributed globally 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variationtrise= 0.35nstskew= 150pstcycle= 3.3nsClock waveformLocation of clockdriver on diepre-driverfinal driversEE14113EE14125EECS141Clock DriversEE14126EECS141Clock Skew in Alpha ProcessorClock Skew in Alpha ProcessorEE14114EE14127EECS141 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width Local clocks can be gated “off” to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checkingtrise= 0.35ns tskew= 50pstcycle= 1.67nsEV6 (Alpha 21264) ClockingEV6 (Alpha 21264) Clocking600 MHz 600 MHz ––0.35 micron CMOS0.35 micron CMOSGlobal clock waveformPLLEE14128EECS14121264 Clocking21264 ClockingEE14115EE14129EECS141EV6 Clock ResultsEV6 Clock ResultsGCLK Skew(at Vdd/2 Crossings)ps5101520253035404550ps300305310315320325330335340345GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)EE14130EECS141EV7 Clock HierarchyEV7 Clock HierarchyGCLK(CPU Core)L2L_CLK(L2 Cache)L2R_CLK(L2 Cache)NCLK(Mem Ctrl)DLLPLLSYSCLKDLLDLL+ widely dispersed drivers+ DLLs compensate static and low-frequency variation+ divides design and verification effort- DLL design and verification is added work+ tailored clocksActive Skew Management and Multiple Clock DomainsEE14116EE14131EECS141Clock AnimationsClock Animations By Phillip Restle (IBM)http://www.research.ibm.com/people/r/restle/Animations/DAC01top.htmlEE14132EECS141Next LectureNext Lecture Power distribution, I/OEE14117EE14133EECS141I/O DesignI/O DesignEE14134EECS141Bonding Pad DesignBonding Pad DesignBonding PadOutInVDDGND100 μmGNDOutEE14118EE14135EECS141ESD ProtectionESD Protection When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate –need guard rings to pick it up.EE14136EECS141ESD ProtectionESD
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