EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 23Lecture 23Sequential LogicSequential LogicTimingTimingEE1412EECS141AnnouncementsAnnouncements Homework 8 due on Thursday Project phase three in lab this week Project reports due on Monday Poster presentations next weekEE1412EE1413EECS141EE1414EECS141EE1413EE1415EECS141Class MaterialClass Material Last lecture Latches and registers Today’s lecture Finish sequential logic Timing Reading Chapter 7, 10EE1416EECS141Other Other Sequential Sequential CircuitsCircuitsEE1414EE1417EECS141Other Sequential CircuitsOther Sequential Circuits Schmitt Trigger Monostable Multivibrators Astable MultivibratorsEE1418EECS141Schmitt TriggerSchmitt TriggerIn OutVinVou tVOHVOLVM–VM+•VTC with hysteresis•Restores signal slopesEE1415EE1419EECS141Noise Suppression using Schmitt TriggerNoise Suppression using Schmitt TriggerEE14110EECS141CMOS Schmitt TriggerCMOS Schmitt TriggerMoves switching thresholdof the first inverter VinM2M1VDDXVoutM4M3EE1416EE14111EECS1412.5VX(V)VM2VM1Vin(V)VCT with hysteresis2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.52.5Vx(V)k= 2k= 3k= 4k= 1Vin(V)2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.5The effect of varying the ratio of the PMOS device M4. The width is k*0.5μm.Schmitt Trigger: Simulated VTCSchmitt Trigger: Simulated VTCEE14112EECS141CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)VDDVDDOutInM1M5M2XM3M4M6EE1417EE14113EECS141Bistable MultivibratorMonostable MultivibratorAstable Multivibratorflip-flop, Schmitt Triggerone-shotoscillatorSRTMultivibratorMultivibratorCircuitsCircuitsEE14114EECS141DELAYtdInOuttdTransitionTransition--Triggered MonostableTriggered MonostableEE1418EE14115EECS141VDDInOutABCRInBOuttVMt2t1(a) Trigger circuit.(b) Waveforms.Monostable Triggered (RCMonostable Triggered (RC--based)based)EE14116EECS141Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)012 N-1simulated response of 5-stage oscillatorEE1419EE14117EECS141Timing Timing DefinitionsDefinitionsEE14118EECS141Synchronous TimingSynchronous TimingCombinationalLogicR1R2CinCoutOutInCLKEE14110EE14119EECS141Latch ParametersLatch ParametersDClkQDQClktc-qtholdPWmtsutd-qDelays can be different for rising and falling data transitionsTEE14120EECS141Register ParametersRegister ParametersDClkQDQClktc-qtholdTtsuDelays can be different for rising and falling data transitionsEE14111EE14121EECS141R1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc − qtc − q, cdtsu, tholdtlogictlogic, cdCycle time: TClk> tc-q+ tlogic+ tsuRace margin: thold< tc-q,cd+ tlogic,cdTiming Constraints Timing Constraints EE14122EECS141Clock Clock NonidealitiesNonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clockingEE14112EE14123EECS141Clock UncertaintiesClock Uncertainties243Power SupplyInterconnect5Temperature6Capacitive Load7Coupling to Adjacent Lines1Clock GenerationDevicesSources of clock uncertaintyEE14124EECS141Clock Skew and JitterClock Skew and Jitter Both skew and jitter affect the effective cycle time Only skew affects the race marginClkClktSKtJSEE14113EE14125EECS141Clock SkewClock Skew# of registersClk delayInsertion delayMax Clk skewEarliest occurrenceof Clk edgeNominal –δ/2Latest occurrenceof Clk edgeNominal +
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