Digital Integrated Circuits © Prentice Hall 2000Sequential LogicEECS 141 – F00Sequential LogicDigital Integrated Circuits © Prentice Hall 2000Sequential LogicSequential LogicFF’sLOGICtp,comb?InOut2 storage mechanisms• positive feedback• charge-basedDigital Integrated Circuits © Prentice Hall 2000Sequential LogicLatch versus Flip-Flop? Latchstores data when clock is low DClkQDClkQ? Flip-Flopstores data when clock rises Clk ClkDDQ QDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPositive Feedback: Bi-StabilityVi1Vo1=Vi2Vo2Vi1Vo2Vo1Vi2 = Vo1Vi2 = Vo1Vi1 = Vo2ACBDigital Integrated Circuits © Prentice Hall 2000Sequential LogicMeta-StabilityVi2 = Vo1Vi1 = Vo2CVi2 = Vo1Vi1 = Vo2B? ?Gain should be larger than 1 in the transition regionDigital Integrated Circuits © Prentice Hall 2000Sequential LogicMux-Based LatchesNegative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)Digital Integrated Circuits © Prentice Hall 2000Sequential LogicMux-Based LatchDD??In??(a) Schematic diagram(b) Non-overlapping clocksPseudo-static LatchDigital Integrated Circuits © Prentice Hall 2000Sequential LogicSR LatchSRQSRQSRQ Q01010011Q100Q010SRQQQSRQSRQQ10101100Q101Q011QQDigital Integrated Circuits © Prentice Hall 2000Sequential LogicCMOS Clocked SR LatchVDDQQRS??M1M3M4M2M6M5 M7M8Digital Integrated Circuits © Prentice Hall 2000Sequential LogicLatch: Transistor Sizing0.0 1.0 2.0 3.0 4.0 5.00.02.04.0VQ(1.8/1.2)(3.6/1.2)(7.2/1.2)Digital Integrated Circuits © Prentice Hall 2000Sequential Logic6 Transistor CMOS SR LatchVDDQQ?M1M3M4M2M5R?SDigital Integrated Circuits © Prentice Hall 2000Sequential LogicRace ProblemQQ?D1tttloop ?Signal can race around during ? = 1Digital Integrated Circuits © Prentice Hall 2000Sequential LogicNLatchLogicLogicPLatch?Latch-Based Design• N latch is transparentwhen ? = 0• P latch is transparent when ? = 1Digital Integrated Circuits © Prentice Hall 2000Sequential LogicMaster-Slave Flip-FlopSRQQQQSRQQJK?MASTERSLAVEQJKQ?PRESETCLEARSIRIDigital Integrated Circuits © Prentice Hall 2000Sequential LogicMux-Based Master-SlaveDigital Integrated Circuits © Prentice Hall 2000Sequential LogicMaster-Slave Flip-FlopDigital Integrated Circuits © Prentice Hall 2000Sequential Logic2-phase dynamic flip-flop????DInInput SampledOutput Enable????Digital Integrated Circuits © Prentice Hall 2000Sequential LogicMaster-Slave Flip-Flop????DInAB??Overlapping Clocks Can Cause• Race Conditions• Undefined SignalsDigital Integrated Circuits © Prentice Hall 2000Sequential Logic2 phase non-overlapping clocks????????DIn????t?12Digital Integrated Circuits © Prentice Hall 2000Sequential Logic2 phase non-overlapping clocksNLatchLogicLogicPLatch??????t?12??NLatchLogicLogicPLatch????Digital Integrated Circuits © Prentice Hall 2000Sequential LogicFlip-flop insensitive to clock overlapDIn?? ??VDDVDDM1M3M4M2 M6M8M7M5??section??sectionCL1CL2XC2MOS LATCHDigital Integrated Circuits © Prentice Hall 2000Sequential LogicC2MOS avoids Race ConditionsDIn1M1M3M2M6M7M51DInVDDVDDM1M4M2 M6M8M50 0VDDVDD(a) (1-1) overlap (b) (0-0) overlapX XDigital Integrated Circuits © Prentice Hall 2000Sequential LogicFlip-Flop: Timing DefinitionsDATASTABLEDATASTABLEInOutttt?tsetuptholdtpFFDigital Integrated Circuits © Prentice Hall 2000Sequential LogicDelay vs. Setup/Hold Times050100150200250300350-200 -150 -100 -50 0 50 100 150 200Data-Clk [ps]Clk-Output [ps]Setup HoldMinimum Data-OutputDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPulse-Triggered LatchesMaster-Slave LatchesDClkQ DClkQClkDataDClkQClkDataPulse-Triggered LatchL1 L2 LFlip-flops:Digital Integrated Circuits © Prentice Hall 2000Sequential LogicPropagation Delay Based Edge-Triggered?InXN2N1Out?InXOuttpLH= Mono-Stable Multi-VibratorDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPulse-Triggered LatchesVddDClkQQHybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :Digital Integrated Circuits © Prentice Hall 2000Sequential LogicPulse-Triggered LatchesClkDQQSR7474, SR latch as a second stageDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPulse-Triggered Latches? First stage is a sense amplifier, precharged to high, when Clk = 0? After rising edge of the clock sense amplifier generates the pulse on S or R? The pulse is captured in S-R latch? Cross-coupled NAND has different propagation delays of rising and falling edgesSense-amplifier-based flip-flop, DEC Alpha 21264, StrongARM 110Digital Integrated Circuits © Prentice Hall 2000Sequential LogicMaximum Clock FrequencyFF’sLOGICtp,comb?Also:tcdreg+ tcdlogic> tholdtcd: contamination delay = minimum delayDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPipeliningREG?REG?REG?log.REG?REG?REG?.REG?REG?logOut Outabab Non-pipelined version Pipelined versionDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPipelined Logic using C2MOS InFOut??VDD??VDD??VDDC2C1GC3NORA CMOSWhat are the constraints on F and G?Digital Integrated Circuits © Prentice Hall 2000Sequential LogicExample 1??VDD??VDDVDDNumber of a static inversions should be evenDigital Integrated Circuits © Prentice Hall 2000Sequential LogicNORA CMOS Modules ??VDDVDDPDN?In1In2In3?VDDPUN??Out??VDDOutVDDPDN?In1In2In3?VDDIn4In4VDD(a)??-module(b)??-moduleCombinational logic LatchDigital Integrated Circuits © Prentice Hall 2000Sequential LogicTSPC - True Single Phase Clock LogicM1M2M3VDDInOut??M1M2M3VDDInOut??M1M2M3VDDInOut?M1M2M3VDDInOut?Precharged NPrecharged PNon-precharged NNon-precharged PDigital Integrated Circuits © Prentice Hall 2000Sequential LogicTSPC - True Single Phase Clock Logic?VDDOut?VDD?VDD?VDDInStaticLogicPUNPDNIncluding logic intothe latchInserting logic betweenlatchesDigital Integrated Circuits © Prentice Hall 2000Sequential LogicDoubled TSPC Latches ?VDDOut?VDDDoubled n-TSPC latchIn?VDDOut?VDDDoubled p-TSPC latchInDigital Integrated Circuits © Prentice Hall 2000Sequential LogicTSPC - True Single Phase Clock Logic?VDDOut?VDD?VDD?VDDInStaticLogicPUNPDNIncluding logic intothe latchInserting logic betweenlatchesDigital Integrated Circuits © Prentice Hall 2000Sequential LogicMaster-Slave TSPC Flip-flops?VDDDVDD?VDDD?VDD?VDDDVDD??D?VDD?VDDDVDD??D(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop (c) Positive edge-triggered D flip-flopusing split-output latches
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