EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 2Lecture 2Design MetricsDesign MetricsEE1412EECS141Administrative StuffAdministrative Stuff Discussions start in week 2 Monday is a holiday Labs start in week 3 Homework #1 is due next Tuesday Everyone should have an EECS instructional account http://www-inst.eecs.berkeley.edu/~inst/newusers.html Use cory, quasar, pulsar PC accounts for 353 Cory will be set up before the first labEE1412EE1413EECS141AnnouncementsAnnouncements Midterms have been moved Midterm 1: October 5 Midterm 2: November 2EE1414EECS141Last LectureLast Lecture Last lecture Introduction, Moore’s law, future of ICs Today’s lecture Introduces basic metrics for design of integrated circuits – how to measure delay, power, cost, etc.EE1413EE1415EECS141Why Scaling?Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But … How to design chips with more and more functions? Design engineering population does not double every two years… Hence, a need for more efficient design methods Exploit different levels of abstractionEE1416EECS141Challenges in Digital DesignChallenges in Digital Design“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.Everything Looks a Little Different“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability•etc.…and There’s a Lot of Them!∝ DSM ∝ 1/DSM?EE1414EE1417EECS141Design Abstraction LevelsDesign Abstraction Levelsn+n+SGD+DEVICECIRCUITGATEMODULESYSTEMEE1418EECS141This ClassThis Class Introduces basic metrics for design of integrated circuits – how to measure delay, power, etc. Groups layout rectangles into transistors and wires Transistors and wires into gates Gates into functions (Functional blocks into systems) – e.g. EECS150 Need to verify that the assumptions are validEE1415EE1419EECS141Design MetricsDesign Metrics How to evaluate performance of a digital circuit (gate, block, …)? Cost Robustness Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a functionEE14110EECS141Cost of Integrated CircuitsCost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip areaEE1416EE14111EECS141Mask Cost is IncreasingMask Cost is Increasing050010001500200025001996 1998 2000 2002 2004 2006 2008YearCost [in $1000]45nm65nm90nm0.13 μm0.18 μm0.25 μmEE14112EECS141Total CostTotal Cost Cost per IC Variable costvolumecost fixed IC percost variable IC percost +=yieldtest finalpackaging ofcost test die ofcost die ofcost cost variable++=EE1417EE14113EECS141Die CostDie CostSingle dieWaferyield die* waferper dies waferofcost die ofcost =From: http://www.amd.comEE14114EECS141Wafer sizeWafer sizeFrom: http://www.sandpile.org8” (200mm)12” (300mm)12” (300mm)90nm CMOS90nm CMOS65nm CMOSAMD AthlonEE1418EE14115EECS141YieldYield%100 waferper chips of number Total waferper chips good of No.×=Yyield Die waferper Diescost Wafercost Die×=()area die2diameter waferarea diediameter/2 wafer waferper Dies2××π−×π=EE14116EECS141DefectsDefectsα−⎟⎠⎞⎜⎝⎛α×+=area dieareaunit per defects1yield dieα is approximately 3 4area) (die cost die f=Yield = 0.25Yield = 0.76EE1419EE14117EECS141Some Examples (1994)Some Examples (1994)$4179%402961.5$15000.803Pentium$27213%482561.6$17000.703Super Sparc$14919%532341.2$15000.703DEC Alpha$7327%661961.0$13000.803HP PA 7100$5328%1151211.3$17000.804Power PC 601$1254%181811.0$12000.803486 DX2$471%360431.0$9000.902386DXDie costYieldDies/waferArea mm2Def./ cm2Wafer costLine widthMetal layersChipEE14118EECS141Cost per TransistorCost per Transistor0.00000010.00000010.0000010.0000010.000010.000010.00010.00010.0010.0010.010.010.10.1111982198219851985198819881991199119941994199719972000200020032003200620062009200920122012cost: cost: ¢¢--perper--transistortransistorFabrication cost per transistorEE14110EE14119EECS141RobustnessRobustness――Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuitsi(t)Inductive coupling Capacitive coupling Power and groundnoisev(t)VDDEE14120EECS141DC OperationDC OperationVoltage Transfer CharacteristicVoltage Transfer CharacteristicV(x)V(y)VOHVOLVMVOHVOLfV(y)=V(x)Switching ThresholdNominal Voltage LevelsVOH = f(VOL)VOL = f(VOH)VM = f(VM)EE14111EE14121EECS141Mapping between analog and digital signalsMapping between analog and digital signalsVILVIHVinSlope = -1Slope = -1VOLVOHVout“0”VOLVILVIHVOHUndefinedRegion“1”EE14122EECS141Definition of Noise MarginsDefinition of Noise MarginsUndefinedRegionNoise margin high:NMH= VOH–VIHNoise margin low:NML= VIL–VOLGate OutputGate InputNMLNMH“0”“1”VOLVOHVILVIH(Stage M) (Stage M+1)EE14112EE14123EECS141Noise BudgetNoise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sourcesEE14124EECS141Key Robustness PropertiesKey Robustness Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric –the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;EE14113EE14125EECS141Regenerative PropertyRegenerative Propertyv0v1v3finv(v)f(v)v3outv2inRegenerativeNon-Regenerativev2v1f(v)finv(v)v3outv0inEE14126EECS141Regenerative PropertyRegenerative PropertyA chain of invertersv0v1v2v3v4v5v62V (Volt)4v0v1v2t (nsec)0⫺11356 8 10Simulated
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