1EE141Interconnect EffectsInput-OutputEE141- Spring 2003Lecture 25EE141Dealing with Capacitive Cross TalkAvoid floating nodesProtect sensitive nodesMake rise and fall times as large as possibleDifferential signalingDo not run wires together for a long distanceUse shielding wiresUse shielding layers2EE141Delay DegradationCc- Impact of neighboring signalactivity on switching delay- When neighboring lines switchin opposite direction of victimline, delay increasesMiller EffectMiller Effect- Both terminals of capacitor are switched in opposite directions(0 → Vdd,Vdd→ 0)- Effective voltage is doubled and additional charge is needed(from Q=CV)EE141Impact of Cross Talk on Delayr is ratio between capacitance to GND and to neighbor3EE141Interconnect ProjectionsLow-k dielectricsBoth delay and power are reduced by dropping interconnectcapacitanceTypes of low-k materials include: inorganic (SiO2), organic(Polyimides) and aerogels (ultra low-k)The numbers below are on theconservative side of the NRTS roadmapGeneration 0.25µm0.18µm0.13µm0.1µm0.07µm0.05µmDielectricConstant3.3 2.7 2.3 2.0 1.8 1.5εεεεEE141How to Battle CapacitiveCrosstalkSubstrate (GND)GNDShieldinglayerVDDGNDShieldingwireAvoid large crosstalk cap’sAvoid floating nodesIsolate sensitive nodesControl rise/fall timesShield!Differential signaling4EE141Driving Large CapacitancesVinVoutCLVDD• Transistor Sizing• Cascaded BuffersEE141Using Cascaded BuffersCL= 20 pFIn Out12 N0.25 µµµµmprocessCin =2.5fFtp0=30psF = CL/Cin= 8000fopt =3.6 N =7tp =0.76ns(See Chapter 5)5EE141Output Driver DesignTrade off Performance for Area and EnergyGiven tpmaxfind N and fAreaEnergy()minminmin121111...1 AfFAffAfffANNdriver−−=−−=++++=−()22212111...1DDLDDiDDiNdriverVfCVCfFVCfffE−≈−−=++++=−EE141Delay as a Function of F and N1013 5 7Number of buffer stages N9 1110,0001000100tp/tp0F=100F=1000F=10,000tp/tp06EE141Output Driver DesignTransistor Sizes for optimally-sized cascaded buffer tp=0.76nsTransistor Sizes of redesigned cascaded buffer tp=1.8ns0.25 µµµµm process, CL=20pFEE141How to Design Large TransistorsG(ate)S(ource)D(rain)MultipleContactssmall transistors in parallelReduces diffusion capacitance7EE141Bonding Pad DesignBonding PadOutInVDDGND100 µmGNDOutEE141ESD ProtectionWhen a chip is connected to a board, there isunknown (potentially large) static voltagedifferenceEqualizing potentials requires (large) chargeflow through the padsDiodes sink this charge into the substrate –need guard rings to pick it up.8EE141ESD ProtectionDiodePADVDDRD1D2XCEE141Chip PackagingChipLL´Bonding wireMountingcavityLeadframePin•Bond wires (~25µm) are usedto connect the package to the chip• Pads are arranged ina framearound the chip• Pads are relatively large(~100µmin0.25µm technology),with large pitch (100µm)•Many chips areas are ‘pad limited’9EE141Pad FrameLayout Die PhotoEE141Chip PackagingAn alternative is ‘flip-chip’:» Pads are distributed around the chip» The soldering balls are placed on pads» The chip is ‘flipped’ onto the package» Can have many more pads10EE141INTERCONNECTDealing with ResistanceEE141Impact of ResistanceImpact of resistance is commonly seen inpower supply distribution:» IR drop» Voltage variationsPower supply is distributed to minimize the IRdrop and the change in current due toswitching of gatesHow to drive long RC wires» Major impact on performance in today’sICs11EE141RI Introduced NoiseVDDXIIR’RVDD- ∆V’∆V∆VφpreEE141Power and Ground DistributionGNDVDDLogicGNDVDDLogicGNDVDD(a) Finger-shaped network (b) Network with multiple supply pins12EE141Resistance and the PowerDistribution ProblemSource: Simplex••Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction••Heavily influenced by packaging technologyHeavily influenced by packaging technologyBeforeBeforeAfterAfterEE141Power DistributionLow-level distribution is in Metal 1Power has to be ‘strapped’ in higher layers ofmetal.The spacing is set by IR drop,electromigration, inductive effectsAlways use multiple contacts on straps13EE141Electromigration (1)Limits dc-current to 1 mA/µmEE141Electromigration (2)14EE141The Impact of ResistivityCN-1CNC2R1R2C1TrVinRN-1RN0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L Diffused signalDiffused signalpropagationpropagationDelay ~ LDelay ~ L22The distributedThe distributedrcrc--linelineEE141The Global Wire Problem(((())))outwwdoutdwwdCRCRCR693.0CR377.0T ++++++++++++====ChallengesNo further improvements to be expected after theintroduction of Copper (superconducting, optical?)Design solutions» Use of fat wires» Insert repeaters — but might become prohibitive (power, area)» Efficient chip floorplanningTowards “communication-based” design» How to deal with latency?» Is synchronicity an absolute necessity?15EE141Interconnect:#ofWiringLayers# of metal layers is steadily increasing due to:• Increasing die size and device count: we need more wires and longer wires to connect everything• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RCsubstratepolyM1M2M3M4M5M6TinsHWSρρρρ =2.2µΩµΩµΩµΩ-cm0.25 µm wiring stackMinimum Widths (Relative)0.00.51.01.52.02.53.03.51.0µ1.0µ1.0µ1.0µ 0.8µ0.8µ0.8µ0.8µ 0.6µ0.6µ0.6µ0.6µ 0.35µ0.35µ0.35µ0.35µ 0.25µ0.25µ0.25µ0.25µM5M4M3M2M1PolyMinimum Spacing (Relative)0.00.51.01.52.02.53.03.54.01.0µ1.0µ1.0µ1.0µ 0.8µ0.8µ0.8µ0.8µ 0.6µ0.6µ0.6µ0.6µ 0.35µ0.35µ0.35µ0.35µ 0.25µ0.25µ0.25µ0.25µM5M4M3M2M1PolyEE141Interconnect Projections:CopperCopper is planned in full sub-0.25µm process flows and large-scaledesigns (IBM, Motorola, IEDM97)With cladding and other effects, Cu~2.2µΩ-cm vs. 3.5 for Al(Cu)⇒40% reduction in resistanceElectromigration improvement;100X longer lifetime (IBM,IEDM97)» Electromigration is a limiting factorbeyond 0.18 µmifAlisused(HP,IEDM95)Vias16EE141Diagonal WiringyxdestinationManhattansourcediagonal•20+% Interconnect length reduction• Clock speedSignal integrityPower integrity• 15+% Smaller chipsplus 30+% via reductionCourtesy Cadence X-initiativeEE141Using BypassesDriverPolysilicon word linePolysilicon word lineMetal word
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