EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 11Lecture 11Wire modelingWire modelingCMOS logicCMOS logicEE1412EECS141AnnouncementsAnnouncements No lab this week Lab 4 reports due next week Hardware lab next week Homework #5 due today No new homework this week Midterm 1 on Thursday, 6:30-8pm, 105 North G. Material until last lecture, homework 5, lab 4 Review session tonight 6-7:30pm, 60 Evans Check the web page for extra office hours There is a lecture on Th No lecture on October 24EE1413EECS141Class MaterialClass Material Last lecture Scaling Wires Today’s lecture Wire models CMOS logic gates Reading (Chapters 4, 6)EE1414EECS141INTERCONNECTINTERCONNECTEE1415EECS141Wire Resistance Wire Resistance WLHR = ρH WLSheet ResistanceRoR1R2EE1416EECS141Interconnect Resistance Interconnect ResistanceEE1412EE1417EECS141Dealing with ResistanceDealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers reduce average wire-lengthEE1418EECS141PolycidePolycideGate MOSFETGate MOSFETn+n+SiO2PolySiliconSilicidepSilicides: WSi2, TiSi2, PtSi2and TaSiConductivity: 8-10 times better than PolyEE1419EECS141Sheet ResistanceSheet ResistanceEE14110EECS141Modern InterconnectModern InterconnectEE14111EECS141Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectricEE14112EECS141Modern InterconnectModern Interconnect 90nm processEE1413EE14113EECS141INTERCONNECTINTERCONNECTEE14114EECS141InterconnectInterconnectModelingModelingEE14115EECS141The Lumped ModelThe Lumped ModelVoutDrivercwi reVinClump edRdriverVoutEE14116EECS141The Lumped RCThe Lumped RC--ModelModelThe Elmore DelayThe Elmore DelayEE14117EECS141The Elmore DelayThe Elmore DelayRC ChainRC ChainEE14118EECS141Wire ModelWire ModelAssume: Wire modeled by N equal-length segments For large values of N:EE1414EE14119EECS141The Distributed RCThe Distributed RC--linelineEE14120EECS141StepStep--response of RC wire as a response of RC wire as a function of time and spacefunction of time and space0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L EE14121EECS141Driving an RCDriving an RC--linelineVinRsVout(rw,cw,L)EE14122EECS141RCRC--ModelsModelsEE14123EECS141CMOS LogicCMOS LogicEE14124EECS141Combinational vs. Sequential LogicCombinational vs. Sequential LogicCombinational SequentialOutput = f(In)Output = f(In, Previous In)CombinationalLogicCircuitOutInCombinationalLogicCircuitOutInStateEE1415EE14125EECS141Static CMOS CircuitStatic CMOS CircuitAt every point in time (except during the switching transients) each gate output is connected to eitherVDDorVssvia a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit style, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. EE14126EECS141Static Complementary CMOSStatic Complementary CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPMOS onlyNMOS onlyPUN and PDN are dual logic networksPUN and PDN functions are complementary ……EE14127EECS141NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel ConnectionTransistor can be thought of as a switch controlled by its gate signalNMOS switch closes when switch control input is highXYABY = X if A AND BXYABY = X if A OR BNMOS Transistors pass a “strong” 0 but a “weak” 1EE14128EECS141PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel ConnectionXYABY = X if AAND B = A + BXYABY = X if AOR B = ABPMOS Transistors pass a “strong” 1 but a “weak” 0PMOS switch closes when switch control input is lowEE14129EECS141Threshold DropsThreshold DropsVDDVDD→ 0PDN0 → VDDCLCLPUNVDD0 → VDD-VTnCLVDDVDDVDD→ |VTp|CLSDSDVGSSSDDVGSEE14130EECS141Next LectureNext Lecture CMOS logic -
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